56F8037/56F8027 Data Sheet Table of Contents
7.3
Product Analysis. . . . . . . . . . . . . . . . . . 131
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
56F8037/56F8027 Features . . . . . . . . . . . 6
56F8037/56F8027 Description . . . . . . . . . 8
Award-Winning Development
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131
Environment . . . . . . . . . . . . . . . . . . . 9
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 18
Data Sheet Conventions. . . . . . . . . . . . . 18
8.1
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . 131
Configuration . . . . . . . . . . . . . . . . . . . . 131
Reset Values . . . . . . . . . . . . . . . . . . . . 135
1.4
1.5
1.6
Part 9 Joint Test Action Group (JTAG) . . .140
Part 2 Signal/Connection Descriptions . . . 19
9.1
56F8037/56F8027 Information . . . . . . . 140
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . 19
56F8037/56F8027 Signal Pins . . . . . . . . 24
Part 10Specifications. . . . . . . . . . . . . . . . . .140
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
General Characteristics . . . . . . . . . . . . 140
DC Electrical Characteristics . . . . . . . . 144
AC Electrical Characteristics . . . . . . . . 147
Flash Memory Characteristics . . . . . . . 148
External Clock Operation Timing . . . . . 148
Phase Locked Loop Timing . . . . . . . . . 149
Relaxation Oscillator Timing. . . . . . . . . 149
Reset, Stop, Wait, Mode Select, and
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . 40
Features . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating Modes . . . . . . . . . . . . . . . . . . 41
Internal Clock Source . . . . . . . . . . . . . . . 42
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42
Ceramic Resonator. . . . . . . . . . . . . . . . . 43
External Clock Input - Crystal Oscillator
Option. . . . . . . . . . . . . . . . . . . . . . . 43
Interrupt Timing . . . . . . . . . . . . . . 151
Serial Peripheral Interface (SPI) Timing152
10.9
3.8
Alternate External Clock Input . . . . . . . . 44
10.10 Quad Timer Timing. . . . . . . . . . . . . . . . 156
10.11 Queued Serial Communication Interface
(QSCI) Timing . . . . . . . . . . . . . . . 158
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44
4.1
4.2
4.3
4.4
4.5
4.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Vector Table . . . . . . . . . . . . . . . 45
Program Map . . . . . . . . . . . . . . . . . . . . . 47
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48
EOnCE Memory Map . . . . . . . . . . . . . . . 50
Peripheral Memory-Mapped Registers . . 51
10.12 Freescale’s Scalable Controller Area
Network (MSCAN) Timing . . . . . . 159
10.13 Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 159
10.14 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161
10.15 Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 162
Part 5 Interrupt Controller (ITCN) . . . . . . . . 68
10.16 Equivalent Circuit for ADC Inputs. . . . . 163
10.17 Comparator (CMP) Parameters . . . . . . 164
10.18 Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 164
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . 68
Features . . . . . . . . . . . . . . . . . . . . . . . . . 68
Functional Description . . . . . . . . . . . . . . 68
Block Diagram. . . . . . . . . . . . . . . . . . . . . 70
Operating Modes . . . . . . . . . . . . . . . . . . 71
Register Descriptions . . . . . . . . . . . . . . . 71
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.19 Power Consumption . . . . . . . . . . . . . . . 166
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168
11.1
56F8037/56F8027 Package and
Pin-Out Information . . . . . . . . . . . 168
Part 6 System Integration Module (SIM). . . 93
Part 12Design Considerations . . . . . . . . . .171
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . 93
Features . . . . . . . . . . . . . . . . . . . . . . . . . 94
Register Descriptions . . . . . . . . . . . . . . . 95
Clock Generation Overview . . . . . . . . . 124
Power-Saving Modes . . . . . . . . . . . . . . 124
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129
12.1
12.2
Thermal Design Considerations . . . . . . 171
Electrical Design Considerations . . . . . 172
Part 13Ordering Information . . . . . . . . . . . .173
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174
Part 7 Security Features. . . . . . . . . . . . . . . 129
7.1
7.2
Operation with Security Enabled. . . . . . 129
Flash Access Lock and Unlock Mechanisms130
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
5
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