Datasheet > 56F803

56F803

更新时间： 2022-11-26 01:19:50

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		控制器
页数	文件大小	规格书
48页	923K
描述
56F803 16-bit Hybrid Controller

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数据手册

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56F803 数据手册

Freescale Semiconductor, Inc.

DSP56F803/D

Rev. 13.0, 02/2004

56F803

Technical Data

56F803 16-bit Hybrid Controller

•

Up to 40 MIPS at 80MHz core frequency

•

Up to 64K × 16-bit words each of external

Program and Data memory

•

DSP and MCU functionality in a unified,

C-efficient architecture

•

6-channel PWM module

•

Hardware DO and REP loops

Two 4-channel 12-bit ADCs

Quadrature Decoder

MCU-friendly instruction set supports both

DSP and controller functions: MAC, bit

manipulation unit, 14 addressing modes

CAN 2.0 B module

Serial Communication Interface (SCI)

Serial Peripheral Interface (SPI)

Up to two General Purpose Quad Timers

•

31.5K × 16-bit words Program Flash

512 × 16-bit words Program RAM

4K × 16-bit words Data Flash

2K × 16-bit words Data RAM

2K × 16-bit words Boot Flash

•

JTAG/OnCE^TMport for debugging

16 shared GPIO lines

100–pin LQFP package

PWM Outputs

PWMA

EXTBOOT

IRQB

Current Sense Inputs

Fault Inputs

RESET

IRQA

VCAPC

SSA

DDA

Digital Reg

JTAG/

OnCE

Port

Analog Reg

Low Voltage

Supervisor

A/D1

A/D2

ADC

VREF

Interrupt

Controller

Data ALU

Quadrature

Decoder 0 /

Quad Timer A

Address

Generation

Unit

Bit

Manipulation

Unit

Program Controller

and

Hardware Looping Unit

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Program Memory

32252 x 16 Flash

512 x 16 SRAM

PAB

PLL

CLKO

•

PDB

16-Bit

56800

Core

•

XTAL

Quad Timer B

Boot Flash

2048 x 16 Flash

Clock Gen

EXTAL

XDB2

Quad Timer C

Quad Timer D

CGDB

Data Memory

4096 x 16 Flash

2048 x 16 SRAM

•

INTERRUPT

CONTROLS

•

XAB1

XAB2

CAN 2.0A/B

•

IPBB

CONTROLS

SCI

A[00:05]

External

Address Bus

Switch

A[06:15] or

GPIO-E2:E3 &

GPIO-A0:A7

COP/

GPIO

COP RESET

Watchdog

External

Bus

Interface

Unit

External

Data Bus

Switch

MODULE CONTROLS

Application-

Specific

Memory &

Peripherals

D[00:15]

IPBus Bridge

(IPBB)

SPI

ADDRESS BUS [8:0]

DATA BUS [15:0]

PS Select

DS Select

WR Enable

RD Enable

Bus

Control

GPIO

*includes TCS pin which is reserved for factory use and is tied to VSS

Figure 1. 56F803 Block Diagram

For More Information On This Product,

Go to: www.freescale.com

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