Datasheet > 554BD000413DG

554BD000413DG

更新时间： 2024-01-01 10:15:47

品牌	Logo	应用领域
芯科 - SILICON		机械振荡器
页数	文件大小	规格书
15页	486K
描述
LVDS Output Clock Oscillator, ROHS COMPLIANT PACKAGE-8

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554BD000413DG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.62	其他特性：	ENABLE/DISABLE FUNCTION; TRAY
最大控制电压：	3.3 V	最小控制电压：
最长下降时间：	0.35 ns	频率调整-机械：	NO
频率偏移/牵引率：	80 ppm	频率稳定性：	50%
JESD-609代码：	e4	线性度：	10%
安装特点：	SURFACE MOUNT	最高工作温度：	85 °C
最低工作温度：	-40 °C	振荡器类型：	LVDS
物理尺寸：	7.0mm x 5.0mm x 1.85mm	最长上升时间：	0.35 ns
最大供电电压：	3.63 V	最小供电电压：	2.97 V
标称供电电压：	3.3 V	表面贴装：	YES
最大对称度：	55/45 %	端子面层：	Gold (Au)
Base Number Matches：	1

554BD000413DG 数据手册

Si554

REVISION D

QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Features



Available with any-rate output



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz

Four selectable output frequencies

Si5602



3rd generation DSPLL with superior



jitter performance

3x better frequency stability than

SAW-based oscillators



Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 10.



SONET/SDH

xDSL

10 GbE LAN / WAN



Low jitter clock generation

Optical modules

Clock and data recovery

Pin Assignments:

See page 9.

Description

The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL circuitry to provide a very low jitter clock for all output frequencies.

(Top View)

The Si554 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si554 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si554 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory-programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

FS[1]

V_C

V_DD

CLK–

CLK+

GND

FS[0]

Functional Block Diagram

V_DD

CLK- CLK+

Any-rate

10–1400 MHz

DSPLL^®

Fixed

Frequency XO

FS0

FS1

Clock Synthesis

ADC

V_c

GND

Rev. 1.2 6/18

Si554

12 3 4 5 6 7...15

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