Datasheet > 54FCT162244T

54FCT162244T

更新时间： 2023-12-20 18:44:21

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
8页	237K
描述
16-Bit Buffer/Line Driver

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数据手册

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54FCT162244T 数据手册

IDT54/74FCT162244T/AT/CT/ET

FASTCMOS16-BITBUFFER/LINEDRIVER

MILITARYANDINDUSTRIALTEMPERATURERANGES

TESTCIRCUITSANDWAVEFORMS

SWITCHPOSITION

Test

Switch

Closed

Open

Open Drain

Disable Low

Enable Low

7.0V

500Ω

All Other Tests

OUT

Pulse

Generator

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

D.U.T.

50pF

Test Circuit for All Outputs

DATA

1.5V

INPUT

LOW-HIGH-LOW

tSU

1.5V

PULSE

1.5V

TIMING

INPUT

ASYNCHRONOUS CONTROL

tREM

PRESET

1.5V

CLEAR

HIGH-LOW-HIGH

PULSE

1.5V

ETC.

SYNCHRONOUS CONTROL

PRESET

1.5V

CLEAR

tSU

Pulse Width

CLOCK ENABLE

ETC.

Set-up, Hold, and Release Times

ENABLE

DISABLE

1.5V

SAME PHASE

CONTROL

INPUT

1.5V

INPUT TRANSITION

PLH

PHL

PZL

tPLZ

VOH

OUTPUT

3.5V

1.5V

3.5V

1.5V

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

VOL

tPLH

0.3V

VOL

1.5V

tPZH

tPHZ

OPPOSITE PHASE

INPUT TRANSITION

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

1.5V

Propagation Delay

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

1...3 4 567 8

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