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54F374LMQB PDF预览

54F374LMQB

更新时间: 2024-01-29 22:38:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动逻辑集成电路触发器
页数 文件大小 规格书
10页 258K
描述
Bus Driver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, CQCC20, CERAMIC, LCC-20

54F374LMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCN, LCC20,.35SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.13
系列:F/FASTJESD-30 代码:S-CQCC-N20
JESD-609代码:e0长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:60000000 Hz最大I(ol):0.02 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):86 mA
传播延迟(tpd):11 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:1.905 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.89 mm
Base Number Matches:1

54F374LMQB 数据手册

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Connection Diagrams  
Pin Assignment for DIP,  
SOIC, SSOP and Flatpak  
Pin Assignment  
for LCC  
DS009524-3  
DS009524-2  
Unit Loading/Fan Out  
Pin  
54F/74F  
Names  
Description  
U.L.  
HIGH/LOW  
1.0/1.0  
Input IIH/IIL  
Output IOH/IOL  
20 µA/−0.6 mA  
20 µA/−0.6 mA  
20 µA/−0.6 mA  
D0–D7  
CP  
Data Inputs  
Clock Pulse Input (Active Rising Edge)  
3-STATE Output Enable Input (Active LOW)  
3-STATE Outputs  
1.0/1.0  
OE  
1.0/1.0  
O0–O7  
150/40 (33.3)  
−3 mA/24 mA (20 mA)  
Functional Description  
Truth Table  
The ’F374 consists of eight edge-triggered flip-flops with in-  
dividual D-type inputs and 3-STATE true outputs. The buff-  
ered clock and buffered Output Enable are common to all  
flip-flops. The eight flip-flops will store the state of their indi-  
vidual D inputs that meet the setup and hold time require-  
ments on the LOW-to-HIGH Clock (CP) transition. With the  
Output Enable (OE) LOW, the contents of the eight flip-flops  
are available at the outputs. When the OE is HIGH, the out-  
puts go to the high impedance state. Operation of the OE in-  
put does not affected the state of the flip-flops.  
Inputs  
Internal  
Output  
Dn  
H
L
CP  
N
N
OE  
L
Register  
On  
H
L
H
L
L
X
X
H
X
Z
=
=
=
=
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
N =  
LOW-to-HIGH Clock Transition  
Logic Diagram  
DS009524-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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