Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
HIGH/LOW Output I /I
OH OL
b
20 mA/ 1.8 mA
CE
CP
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
50/33.3
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
P –P
0
3
PL
Asynchronous Parallel Load Input (Active LOW)
Up/Down Count Control Input
Flip-Flop Outputs
U/D
b
b
b
Q –Q
0
1 mA/20 mA
1 mA/20 mA
1 mA/20 mA
3
RC
TC
Ripple Clock Output (Active LOW)
Terminal Count Output (Active HIGH)
Functional Description
The ’F191 is a synchronous up/down 4-bit binary counter. It
contains four edge-triggered flip-flops, with internal gating
and steering logic to provide individual preset, count-up and
count-down operations.
A method of causing state changes to occur simultaneously
in all stages is shown in Figure 2. All clock inputs are driven
in parallel and the RC outputs propagate the carry/borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the neg-
ative-going edge of the carry/borrow signal to ripple through
to the last stage before the clock goes HIGH. There is no
such restriction on the HIGH state duration of the clock,
since the RC output of any device goes HIGH shortly after
its CP input goes HIGH.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information pres-
ent on the Parallel Data inputs (P –P ) is loaded into the
3
0
counter and appears on the Q outputs. This operation over-
rides the counting functions, as indicated in the Mode Se-
lect Table.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The sim-
ple inhibit scheme of Figures 1 and 2 doesn’t apply, be-
cause the TC output of a given stage is not affected by its
own CE.
A HIGH signal on the CE input inhibits counting. When CE is
LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction
of counting is determined by the U/D input signal, as indi-
cated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that the
recommended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-
down mode or reaches 15 in the count-up mode. The TC
output will then remain HIGH until a state change occurs,
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal be-
cause it is subject to decoding spikes.
Mode Select Table
Inputs
Mode
PL
CE
U/D
CP
H
H
L
L
L
L
H
X
X
L
L
X
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
X
H
H
X
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, the RC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again. This feature simplifies the design of
multistage counters, as indicated in Figures 1 and 2. In Fig-
ure 1, each RC output is used as the clock input for the next
higher stage. This configuration is particularly advantageous
when the clock source has a limited drive capability, since it
drives only the first stage. To prevent counting in all stages
it is only necessary to inhibit the first stage, since a HIGH
signal on CE inhibits the RC output pulse, as indicated in the
RC Truth Table. A disadvantage of this configuration, in
some applications, is the timing skew between state chang-
es in the first and last stages. This represents the cumula-
tive delay of the clock as it ripples through the preceding
stages.
RC Truth Table
Inputs
Output
RC
CE
TC*
CP
L
H
X
H
X
L
ß
X
ß
H
X
H
*TC is generated internally
e
e
e
L
ß
H
HIGH Voltage Level
LOW Voltage Level
Immaterial
L
X
e
e
LOW-to-HIGH Clock Transition
LOW Pulse
2
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