54F175LM

更新时间： 2024-01-08 20:18:51

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器逻辑集成电路
页数	文件大小	规格书
8页	170K
描述
Quad D Flip-Flop

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技术参数
数据手册

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54F175LM 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.73
Is Samacsys：	N	Base Number Matches：	1

54F175LM 数据手册

Unit Loading/Fan Out

54F/74F

Pin Names

Description

U.L.

Input I /I

IH IL

Output I /I

HIGH/LOW

OH OL

20 mA/ 0.6 mA

D –D

Data Inputs

1.0/1.0

50/33.3

Clock Pulse Input (Active Rising Edge)

Master Reset Input (Active LOW)

True Outputs

Q –Q

1 mA/20 mA

Q –Q

Complement Outputs

Functional Description

Truth Table

The ’F175 consists of four edge-triggered D flip-flops with

individual D inputs and Q and Q outputs. The Clock and

Master Reset are common. The four flip-flops will store the

state of their individual D inputs on the LOW-to-HIGH clock

(CP) transition, causing individual Q and Q outputs to follow.

A LOW input on the Master Reset (MR) will force all Q out-

puts LOW and Q outputs HIGH independent of Clock or

Data inputs. The ’F175 is useful for general logic applica-

tions where a common Master Reset and Clock are accept-

able.

Inputs

Outputs

HIGH Voltage Level

LOW Voltage Level

Immaterial

LOW-to-HIGH Clock Transition

Logic Diagram

TL/F/9490–4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

123 4 5 6 7 8

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