54F175DMQB

更新时间： 2024-02-03 15:42:10

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器
页数	文件大小	规格书
23页	1410K
描述
LMP91050 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications

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技术参数
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54F175DMQB 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.73
Is Samacsys：	N	Base Number Matches：	1

54F175DMQB 数据手册

LMP91050

www.ti.com

SNAS517D –NOVEMBER 2011–REVISED MARCH 2013

Electrical Characteristics⁽¹⁾(continued)

The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for T_A= -40°C to +85°C unless otherwise

specified. All other limits apply to T_A= T_J= +25°C.

(2)

(3)

(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Programmable Gain Amplifier (PGA) 2nd Stage, R_S= 1kΩ, C_L= 1µF

VINMAX

VINMIN

Max input signal

Min input signal

Gain

GAIN = 4 V/V

1.65

0.82

Programmable in 4 steps

Any gain

V/V

Gain Error

2.5

VDD –

0.2

VOUT

Output Voltage Range

Phase Delay

0.2

100mV input sine 35kHz signal, Gain = 8, VOUT

measured at 1.65V, R_L= 10kΩ

PhDly

µs

Phase Delay variation with

Temperature

250mV input step signal, Gain = 8, Vout

measured at Vdd/2

TCPhDly

SSBW

Cin

Small Signal Bandwidth

Input Capacitance

Gain = 32 V/V

360

kHz

CLOAD,

OUT

OUT Pin Load Capacitance

OUT Pin Load Resistance

Series RC

µF

RLOAD,

OUT

kΩ

Combined Amplifier Chain Specification

Combination of both current and voltage noise,

with a 86kΩ source impedance at 5Hz, Gain =

7986

en Input-Referred Noise Density

nV/√Hz

Combination of both current and voltage noise,

Input-Referred Integrated Noise with a 86kΩ source impedance 0.1Hz to 10Hz,

0.12

0.1

µVrms

(4)

Gain = 7986

PGA1 GAIN = 42, PGA2 GAIN = 4

PGA1 GAIN = 42, PGA2 GAIN = 8

PGA1 GAIN = 42, PGA2 GAIN = 16

167

335

669

PGA1 GAIN = 42, PGA2 GAIN = 32

1335

1002

2004

4003

7986

Gain

V/V

PGA1 GAIN = 250, PGA2 GAIN = 4

PGA1 GAIN = 250, PGA2 GAIN = 8

PGA1 GAIN = 250, PGA2 GAIN = 16

PGA1 GAIN = 250, PGA2 GAIN = 32

Gain Error

Any gain

ppm/°C

(5)

TCCGE

PSRR

Gain Temp Coefficient

100

500

Power Supply Rejection Ratio

DC, 3.0V to 3.6V supply, gain = 1002V/V

110

1mV input step signal, Gain = 1002, Vout

measured at Vdd/2

PhDly

Phase Delay

µs

Phase Delay variation with

Temperature

1mV input step signal, Gain=1002, Vout

measured at Vdd/2

TCPhDly

(6)

(4) Specified by design and characterization. Not tested on shipped production material.

(5) TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear

interpolation.

(6) TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements.

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