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54F174FM PDF预览

54F174FM

更新时间: 2024-02-13 16:50:51
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 168K
描述
Hex D Flip-Flop with Master Reset

54F174FM 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.73
Is Samacsys:NBase Number Matches:1

54F174FM 数据手册

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Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
Output I /I  
HIGH/LOW  
OH OL  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
D D  
0
Data Inputs  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33.3  
5
CP  
Clock Pulse Input (Active Rising Edge)  
Master Reset Input (Active LOW)  
Outputs  
MR  
b
Q Q  
0
1 mA/20 mA  
5
Functional Description  
Truth Table  
The ’F174 consists of six edge-triggered D flip-flops with  
individual D inputs and Q outputs. The Clock (CP) and Mas-  
ter Reset (MR) are common to all flip-flops. Each D input’s  
state is transferred to the corresponding flip-flop’s output  
following the LOW-to-HIGH Clock (CP) transition. A LOW  
input to the Master Reset (MR) will force all outputs LOW  
independent of Clock or Data inputs. The ’F174 is useful for  
applications where the true output only is required and the  
Clock and Master Reset are common to all storage ele-  
ments.  
Inputs  
Outputs  
MR  
CP  
D
Q
n
n
L
H
H
X
X
L
L
L
H
L
H
L
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
e
L
LOW-to-HIGH Clock Transition  
Logic Diagram  
TL/F/9489–4  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
2

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