54F161AFMQR

更新时间： 2024-01-31 03:20:15

品牌	Logo	应用领域
德州仪器 - TI		计数器
页数	文件大小	规格书
12页	431K
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54F161AFMQR 数据手册

Functional Description

The ’F161A and ’F163A count in modulo-16 binary se-

quence. From state 15 (HHHH) they increment to state 0

(LLLL). The clock inputs of all flip-flops are driven in parallel

through a clock buffer. Thus all changes of the Q outputs

(except due to Master Reset of the ’F161A) occur as a re-

sult of, and synchronous with, the LOW-to-HIGH transition

of the CP input signal. The circuits have four fundamental

modes of operation, in order of precedence: asynchronous

reset (’F161A), synchronous reset (’F163A), parallel load,

count-up and hold. Five control inputsÐMaster Reset (MR,

’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable

(PE), Count Enable Parallel (CEP) and Count Enable Trickle

(CET)Ðdetermine the mode of operation, as shown in the

Mode Select Table. A LOW signal on MR overrides all other

inputs and asynchronously forces all outputs LOW. A LOW

signal on SR overrides counting and parallel loading and

allows all outputs to go LOW on the next rising edge of CP.

A LOW signal on PE overrides counting and allows informa-

flip-flops on the next rising edge of CP. With PE and MR

(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-

ing when both are HIGH. Conversely, a LOW signal on ei-

ther CEP or CET inhibits counting.

The ’F161A and ’F163A use D-type edge triggered flip-flops

and changing the SR, PE, CEP and CET inputs when the CP

is in either state does not cause errors, provided that the

recommended setup and hold times, with respect to the ris-

ing edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH

and the counter is in state 15. To implement synchronous

multi-stage counters, the TC outputs can be used with the

CEP and CET inputs in two different ways. Please refer to

the ’F568 data sheet. The TC output is subject to decoding

spikes due to internal race conditions and is therefore not

recommended for use as a clock or asynchronous reset for

flip-flops, counters or registers.

Logic Equations: Count Enable

CEP CET PE

CET

tion on the Parallel Data (P ) inputs to be loaded into the

State Diagram

Mode Select Table

Action on the Rising

*SR

CET

CEP

Clock Edge (L)

Reset (Clear)

^{Load (P}_nxQ )

Count (Increment)

No Change (Hold)

*For ’F163A only

HIGH Voltage Level

LOW Voltage Level

Immaterial

TL/F/9486–5

Obsolete

1 2 345 6 7...12

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