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54ACTQ533F PDF预览

54ACTQ533F

更新时间: 2024-02-01 09:05:22
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
8页 159K
描述
Quiet Series Octal Transparent Latch with TRI-STATE Outputs

54ACTQ533F 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
系列:ACTJESD-30 代码:S-CQCC-N20
JESD-609代码:e0长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):10.5 ns认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:1.905 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

54ACTQ533F 数据手册

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Connection Diagrams  
Pin Assignment  
for DIP and Flatpak  
Pin Assignment  
for LCC  
DS100241-4  
DS100241-3  
Functional Description  
Truth Table  
The ACTQ533 contains eight D-type latches with TRI-STATE  
standard outputs. When the Latch Enable (LE) input is  
HIGH, data on the Dn inputs enters the latches. In this con-  
dition the latches are transparent, i.e., a latch output will  
change state each time its D input changes. When LE is  
LOW, the latches store the information that was present on  
the D inputs a setup time preceding the HIGH-to-LOW tran-  
sition of LE. The TRI-STATE standard outputs are controlled  
by the Output Enable (OE) input. When OE is LOW, the stan-  
dard outputs are in the 2-state mode. When OE is HIGH, the  
standard outputs are in the high impedance mode but this  
does not interfere with entering new data into the latches.  
Inputs  
Outputs  
LE  
X
OE  
H
L
Dn  
On  
Z
X
L
H
H
L
H
L
H
X
L
L
O0  
=
=
=
=
H
L
Z
X
O
HIGH Voltage Level  
LOW Voltage Level  
High Impedance  
Immaterial  
=
Previous O before HIGH to Low transition of Latch Enable  
0
0
Logic Diagram  
DS100241-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.national.com  
2

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