Datasheet > 54ACTQ533LM

54ACTQ533LM

更新时间： 2024-02-09 16:18:07

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德州仪器 - TI		/
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8页	150K
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54ACTQ533LM 数据手册

August 1998

54ACTQ533

Quiet Series Octal Transparent Latch with TRI-STATE^®

Outputs

General Description

Features

n I_CCand I_OZreduced by 50%

The ACTQ533 consists of eight latches with TRI-STATE out-

puts for bus organized system applications. The flip-flops ap-

pear transparent to the data when Latch Enable (LE) is

HIGH. When LE is low, the data satisfying the input timing re-

quirements is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the bus out-

put is in the high impedance state.

n Guaranteed simultaneous switching noise level and

dynamic threshold performance

n Improved latch up immunity

n Eight latches in a single package

n TRI-STATE outputs drive bus lines or buffer memory

address registers

The ACTQ533 utilizes NSC Quiet Series technology to guar-

antee quiet output switching and improve dynamic threshold

n Outputs source/sink 24 mA

n Inverted version of the ACTQ373

n 4 kV minimum ESD immunity

™

performance. FACT Quiet Series features GTO output

control and undershoot corrector in addition to a split ground

bus for superior performance.

Logic Symbols

IEEE/IEC

DS100241-1

DS100241-2

Description

Names

D₀–D₇

Data Inputs

Latch Enable Input

Output Enable Input

O₀–O₇

TRI-STATE Latch

Outputs

™

GTO is a trademark of National Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

FACT^®is a registered trademark of Fairchild Semiconductor Corporation.

™

FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.

DS100241

www.national.com

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