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54ACT373D PDF预览

54ACT373D

更新时间: 2024-02-10 18:27:32
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
10页 169K
描述
Octal Transparent Latch with TRI-STATE Outputs

54ACT373D 技术参数

生命周期:Obsolete包装说明:QCCN,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57系列:ACT
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):12.5 ns认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:1.905 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

54ACT373D 数据手册

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Connection Diagrams  
Pin Assignment for LCC  
Pin Assignment for DIP  
and Flatpak  
DS100329-4  
DS100329-3  
Functional Description  
The ’AC/’ACT373 contains eight D-type latches with  
TRI-STATE standard outputs. When the Latch Enable (LE)  
input is HIGH, data on the Dn inputs enters the latches. In  
this condition the latches are transparent, i.e., a latch output  
will change state each time its D input changes. When LE is  
LOW, the latches store the information that was present on  
the D inputs a setup time preceding the HIGH-to-LOW tran-  
sition of LE. The TRI-STATE standard outputs are controlled  
by the Output Enable (OE) input. When OE is LOW, the stan-  
dard outputs are in the 2-state mode. When OE is HIGH, the  
standard outputs are in the high impedance mode but this  
does not interfere with entering new data into the latches.  
Truth Table  
Inputs  
Outputs  
LE  
X
OE  
H
L
Dn  
X
On  
Z
H
H
L
L
L
L
H
X
H
L
O0  
=
=
=
=
H
L
Z
X
O
HIGH Voltage Level  
LOW Voltage Level  
High Impedance  
Immaterial  
=
Previous O before HIGH to Low transition of Latch Enable  
0
0
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