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54ACT175 PDF预览

54ACT175

更新时间: 2024-01-11 06:34:42
品牌 Logo 应用领域
其他 - ETC 触发器
页数 文件大小 规格书
8页 145K
描述
Quad D Flip-Flop

54ACT175 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41系列:ACT
JESD-30 代码:R-GDFP-F16长度:9.6645 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:95000000 Hz最大I(ol):0.024 A
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
传播延迟(tpd):12.5 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class Q座面最大高度:2.032 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:6.604 mm
最小 fmax:95 MHzBase Number Matches:1

54ACT175 数据手册

 浏览型号54ACT175的Datasheet PDF文件第1页浏览型号54ACT175的Datasheet PDF文件第3页浏览型号54ACT175的Datasheet PDF文件第4页浏览型号54ACT175的Datasheet PDF文件第5页浏览型号54ACT175的Datasheet PDF文件第6页浏览型号54ACT175的Datasheet PDF文件第7页 
Functional Description  
Truth Table  
The ’AC/’ACT175 consists of four edge-triggered D flip-flops  
with individual D inputs and Q and Q outputs. The Clock and  
Master Reset are common. The four flip-flops will store the  
state of their individual D inputs on the LOW-to-HIGH clock  
(CP) transition, causing individual Q and Q outputs to follow.  
A LOW input on the Master Reset (MR) will force all Q out-  
puts LOW and Q outputs HIGH independent of Clock or Data  
inputs. The ’AC/’ACT175 is useful for general logic applica-  
Inputs  
Outputs  
=
@
@
tn+1  
tn, MR  
H
Dn  
L
Qn  
L
Qn  
H
H
H
L
=
=
=
H
L
HIGH Voltage Level  
LOW Voltage Level  
Bit Time before Clock Pulse  
Bit Time after Clock Pulse  
tions where  
acceptable.  
a common Master Reset and Clock are  
t
t
n
=
n+1  
Logic Diagram  
DS100278-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.national.com  
2

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