54ACT169L

更新时间： 2024-01-24 23:36:09

品牌	Logo	应用领域
美国国家半导体 - NSC		计数器
页数	文件大小	规格书
10页	187K
描述
4-Stage Synchronous Bidirectional Counter

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54ACT169L 技术参数

Connection Diagrams

Pin Assignment

for DIP and Flatpak

Pin Assignment

for LCC

DS100276-3

DS100276-4

Logic Diagram

DS100276-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

data on the P₀–P₃inputs enters the flip-flops on the next ris-

ing edge of the Clock. In order for counting to occur, both

CEP and CET must be LOW and PE must be HIGH; the U/D

input then determines the direction of counting. The Terminal

Count (TC) output is normally HIGH and goes LOW, pro-

vided that CET is LOW, when a counter reaches zero in the

Count Down mode or reaches 15 in the Count Up mode. The

TC output state is not a function of the Count Enable Parallel

(CEP) input level. If an illegal state occurs, the ’AC169 will

return to the legitimate sequence within two counts. Since

Functional Description

The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops

and have no constraints on changing the control or data in-

put signals in either state of the Clock. The only requirement

is that the various inputs attain the desired state at least a

setup time before the rising edge of the clock and remain

valid for the recommended hold time thereafter. The parallel

load operation takes precedence over the other operations,

as indicated in the Mode Select Table. When PE is LOW, the

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