54ACT16823

更新时间： 2022-12-13 12:55:17

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
8页	130K
描述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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数据手册

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54ACT16823 数据手册

54ACT16823, 74ACT16823

18-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS160A – APRIL 1991 – REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION

2 × V

Open

GND

TEST

Open

PLH PHL

500 Ω

From Output

Under Test

2 × V

GND

PLZ PZL

PHZ PZH

= 50 pF

500 Ω

(see Note A)

LOAD CIRCUIT

3 V

0 V

Timing Input

Data Input

1.5 V

3 V

0 V

Input

1.5 V

0 V

VOLTAGE WAVEFORMS

Output

Control

(low-level

enabling)

3 V

0 V

3 V

0 V

1.5 V

Input

1.5 V

PZL

PHL

PLH

PLZ

Output

Waveform 1

In-Phase

Output

50% V

20% V

S1 at 2 × V

(see Note B)

PHZ

PLH

PHL

PZH

Output

Waveform 2

S1 at GND

0 V

Out-of-Phase

Output

80% V

50% V

(see Note B)

VOLTAGE WAVEFORMS

includes probe and jig capacitance.

VOLTAGE WAVEFORMS

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1...4 5 678

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