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532RA1134M000G PDF预览

532RA1134M000G

更新时间: 2024-10-02 07:44:11
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芯科 - SILICON /
页数 文件大小 规格书
12页 204K
描述
Oscillator

532RA1134M000G 数据手册

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Si532  
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)  
(10 MHZ TO 1.4 GHZ)  
Features  
Available with any-rate output  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
frequencies from 10 MHz to 945 MHz  
and select frequencies to 1.4 GHz  
Two selectable output frequencies Available CMOS, LVPECL,  
®
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 7.  
SONET/SDH  
Networking  
SD/HD video  
Test and measurement  
Clock and data recovery  
FPGA/ASIC clock generation  
Pin Assignments:  
See page 6.  
Description  
(Top View)  
The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced  
®
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si532 is  
VDD  
1
2
3
6
5
4
FS  
OE  
available with any-rate output frequency from 10 to 945 MHz and select  
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is  
required for each output frequency, the Si532 uses one fixed crystal  
frequency to provide a wide range of output frequencies. This IC based  
approach allows the crystal resonator to provide exceptional frequency  
stability and reliability. In addition, DSPLL clock synthesis provides superior  
supply noise rejection, simplifying the task of generating low jitter clocks in  
noisy environments typically found in communication systems. The Si532 IC  
based XO is factory configurable for a wide variety of user specifications  
including frequency, supply voltage, output format, and temperature stability.  
Specific configurations are factory programmed at time of shipment, thereby  
eliminating long lead times associated with custom oscillators.  
CLK–  
CLK+  
GND  
(LVDS/LVPECL/CML)  
VDD  
1
2
3
6
5
4
FS  
OE  
NC  
Functional Block Diagram  
GND  
CLK  
VDD  
CLK– CLK+  
(CMOS)  
Any-rate  
10–1400 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock  
Synthesis  
FS  
OE  
GND  
Rev. 1.0 7/06  
Copyright © 2006 by Silicon Laboratories  
Si532  

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