Datasheet > 530HA1225M00DGR

530HA1225M00DGR

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	111K
描述
CMOS/TTL Output Clock Oscillator, 1225MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530HA1225M00DGR 数据手册

Si530/531

Revision 1.1 to Revision 1.2

DOCUMENT CHANGE LIST

Revision 0.4 to Revision 0.5

 Updated 2.5 V/3.3 V and 1.8 V CML output level

specifications for Table 3 on page 3.

 Updated Table 1, “Recommended Operating

 Added footnotes clarifying max offset frequency test

Conditions,” on page 2.

conditions for Table 4 on page 4.

Added maximum supply current specifications.

Specified relationship between temperature at startup

and operation temperature.

 Added CMOS phase jitter specs to Table 4 on

page 4.

 Removed the words "Differential Modes:

LVPECL/LVDS/CML" in the footnote referring to

AN256 in Table 4 on page 4.

 Updated Table 4, “CLK± Output Phase Jitter,” on

page 4 to include maximum rms jitter generation

specifications and updated typical rms jitter

specifications.

 Separated 1.8 V, 2.5 V/3.3 V supply voltage

specifications in Table 8 on page 5.

 Added Table 6, “CLK± Output Phase Noise

 Updated and clarified Table 8 on page 5 to include

the "Moisture Sensitivity Level" and "Contact Pads"

rows.

(Typical),” on page 4.

 Added Output Enable active polarity as an option in

Figure 1, “Part Number Convention,” on page 7.

 Updated Figure 3 on page 9 and Table 12 on page 9

to reflect specific marking information. Previously,

Figure 3 was generic.

Revision 0.5 to Revision 1.0

 Updated Note 3 in Table 1, “Recommended

Operating Conditions,” on page 2.

 Updated Figure 1, “Part Number Convention,” on

page 7.

Revision 1.0 to Revision 1.1

 Updated Table 1, “Recommended Operating

Conditions,” on page 2.

Device maintains stable operation over –40 to +85 ºC

operating temperature range.

Supply current specifications updated for revision D.

 Updated Table 2, “CLK± Output Frequency

Characteristics,” on page 2.

Added specification for ±20 ppm lifetime stability

(±7 ppm temperature stability) XO.

 Updated Table 3, “CLK± Output Levels and

Symmetry,” on page 3.

Updated LVDS differential peak-peak swing

specifications.

 Updated Table 4, “CLK± Output Phase Jitter,” on

page 4.

 Updated Table 5, “CLK± Output Period Jitter,” on

page 4.

Revised period jitter specifications.

 Updated Table 8, “Absolute Maximum Ratings ,” on

page 5 to reflect the soldering temperature time at

260 ºC is 20–40 sec per JEDEC J-STD-020C.

 Updated 3. "Ordering Information" on page 7.

Changed ordering instructions to revision D.

 Added 5. "Si530/Si531 Mark Specification" on page

Rev. 1.2

1...8 9 101112

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