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530DB1218M00DGR PDF预览

530DB1218M00DGR

更新时间: 2024-01-25 22:22:31
品牌 Logo 应用领域
芯科 - SILICON 机械振荡器
页数 文件大小 规格书
12页 111K
描述
CMOS/TTL Output Clock Oscillator, 1218MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530DB1218M00DGR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:unknown
风险等级:5.57其他特性:TAPE AND REEL
最长下降时间:0.35 ns频率调整-机械:NO
频率稳定性:20%JESD-609代码:e4
安装特点:SURFACE MOUNT标称工作频率:1218 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:CMOS/TTL物理尺寸:7.0mm x 5.0mm x 1.85mm
最长上升时间:0.35 ns最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES最大对称度:55/45 %
端子面层:Nickel/Gold (Ni/Au)Base Number Matches:1

530DB1218M00DGR 数据手册

 浏览型号530DB1218M00DGR的Datasheet PDF文件第6页浏览型号530DB1218M00DGR的Datasheet PDF文件第7页浏览型号530DB1218M00DGR的Datasheet PDF文件第8页浏览型号530DB1218M00DGR的Datasheet PDF文件第9页浏览型号530DB1218M00DGR的Datasheet PDF文件第10页浏览型号530DB1218M00DGR的Datasheet PDF文件第12页 
Si530/531  
Revision 1.1 to Revision 1.2  
DOCUMENT CHANGE LIST  
Revision 0.4 to Revision 0.5  
Updated 2.5 V/3.3 V and 1.8 V CML output level  
specifications for Table 3 on page 3.  
Updated Table 1, “Recommended Operating  
Added footnotes clarifying max offset frequency test  
Conditions,” on page 2.  
conditions for Table 4 on page 4.  
Added maximum supply current specifications.  
Specified relationship between temperature at startup  
and operation temperature.  
Added CMOS phase jitter specs to Table 4 on  
page 4.  
Removed the words "Differential Modes:  
LVPECL/LVDS/CML" in the footnote referring to  
AN256 in Table 4 on page 4.  
Updated Table 4, “CLK± Output Phase Jitter,” on  
page 4 to include maximum rms jitter generation  
specifications and updated typical rms jitter  
specifications.  
Separated 1.8 V, 2.5 V/3.3 V supply voltage  
specifications in Table 8 on page 5.  
Added Table 6, “CLK± Output Phase Noise  
Updated and clarified Table 8 on page 5 to include  
the "Moisture Sensitivity Level" and "Contact Pads"  
rows.  
(Typical),” on page 4.  
Added Output Enable active polarity as an option in  
Figure 1, “Part Number Convention,” on page 7.  
Updated Figure 3 on page 9 and Table 12 on page 9  
to reflect specific marking information. Previously,  
Figure 3 was generic.  
Revision 0.5 to Revision 1.0  
Updated Note 3 in Table 1, “Recommended  
Operating Conditions,” on page 2.  
Updated Figure 1, “Part Number Convention,” on  
page 7.  
Revision 1.0 to Revision 1.1  
Updated Table 1, “Recommended Operating  
Conditions,” on page 2.  
Device maintains stable operation over –40 to +85 ºC  
operating temperature range.  
Supply current specifications updated for revision D.  
Updated Table 2, “CLK± Output Frequency  
Characteristics,” on page 2.  
Added specification for ±20 ppm lifetime stability  
(±7 ppm temperature stability) XO.  
Updated Table 3, “CLK± Output Levels and  
Symmetry,” on page 3.  
Updated LVDS differential peak-peak swing  
specifications.  
Updated Table 4, “CLK± Output Phase Jitter,” on  
page 4.  
Updated Table 5, “CLK± Output Period Jitter,” on  
page 4.  
Revised period jitter specifications.  
1
Updated Table 8, “Absolute Maximum Ratings ,” on  
page 5 to reflect the soldering temperature time at  
260 ºC is 20–40 sec per JEDEC J-STD-020C.  
Updated 3. "Ordering Information" on page 7.  
Changed ordering instructions to revision D.  
Added 5. "Si530/Si531 Mark Specification" on page  
9.  
Rev. 1.2  
11  

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