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501CAA100M000BAGR

更新时间： 2024-02-25 08:33:39
品牌 Logo 应用领域
芯科 - SILICON 机械石英晶振振荡器
页数 文件大小 规格书
7页 505K
描述
LVCMOS Output Clock Oscillator, 0.032MHz Min, 100MHz Max, 100MHz Nom, CMOS, DFN-4

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501CAA100M000BAGR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：DILCC4,.12Reach Compliance Code：unknown
风险等级：5.84其他特性：ENABLE/DISABLE FUNCTION; TR
最长下降时间：1.6 ns频率调整-机械：NO
频率稳定性：50%JESD-609代码：e4
安装特点：SURFACE MOUNT端子数量：4
最大工作频率：100 MHz最小工作频率：0.032 MHz
标称工作频率：100 MHz最高工作温度：85 °C
最低工作温度：-40 °C振荡器类型：LVCMOS
输出负载：15 pF封装主体材料：PLASTIC/EPOXY
封装等效代码：DILCC4,.12物理尺寸：5.0mm x 3.2mm x 0.9mm
电源：2.5 V认证状态：Not Qualified
最长上升时间：1.6 ns子类别：XO, Clock
最大压摆率：8.9 mA标称供电电压：2.5 V
表面贴装：YES最大对称度：55/45 %
技术：CMOS端子面层：Gold (Au) - with Nickel (Ni) barrier
Base Number Matches：1

501CAA100M000BAGR 数据手册

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Si501/2/3/4  
LVCMOS CMEMS® Programmable Oscillator Series  
6. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable.  
Selected Electrical Specifications  
VDD = +1.71 V to +3.63 V, TA = -40 to 85 ºC unless stated otherwise.  
Parameter  
Frequency Range  
Supply Voltage  
Symbol  
FCLK  
VDD  
Test Condition/Comment  
Programmable family range  
Min  
0.032  
1.71  
—
—
—
—
—
—
-20  
-30  
-50  
0.4  
1
2
4
7
Typ  
—
—
1.7  
3.9  
1.7  
3.9  
670  
0.3  
—
—
—
0.7  
1.3  
3
Max  
100  
3.63  
2.5  
4.9  
2.5  
4.9  
890  
1
+20  
+30  
+50  
1.2  
1.6  
4
Unit  
MHz  
V
mA  
mA  
mA  
mA  
A  
Supports continuous VDD from Min to Max  
3.3 VDD, FCLK = 1 MHz, 4 pF, Low Power mode  
3.3 VDD, FCLK = 1 MHz, 4 pF, Low Jitter mode  
Stop mode, FCLK = 1 MHz, Low Power mode  
Stop mode, FCLK = 1 MHz, Low Jitter mode  
Doze mode  
Supply Current  
IDD1  
Static Supply Current1  
Frequency Stability2  
IDD2  
Sleep mode  
A  
ppm  
ppm  
ppm  
ns  
ns  
ns  
FSTAB  
TA = -20 ºC to +70 ºC, -40 ºC to +85 ºC  
1st option code = A4 or H4  
1st option code = B, C, D, J, K, L  
1st option code = E, M  
CMOS Rise/Fall Time3  
TR/TF  
1st option code = F, N  
5
8
7
11  
ns  
ns  
1st option code = G, P  
FCLK = 100 MHz, Low Jitter mode  
Cycle-to-Cycle Jitter  
Period Jitter Pk-Pk  
Period Jitter  
JCCPP  
JPPKPK  
JPRMS  
—
—
—
—
45  
14  
9
25  
13  
ps pk-pk  
ps pk-pk  
ps rms  
ps rms  
%
1st option code = H  
FCLK = 100 MHz, Low Jitter mode  
1st option code = H  
FCLK = 100 MHz, Low Jitter mode  
1
1.6  
1.3  
55  
1st option code = H  
FCLK = 75 MHz, FOFFSET = 900 kHz - 7.5 MHz  
Low Jitter mode, 1st option code = H  
Drive strength selected such that TR/TF  
(20% to 80%) < 10 % of period  
Phase Jitter5  
1
Duty Cycle  
DC  
50  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
VIH  
VIL  
VOH  
VOL  
0.7 x VDD  
—
0.9 x VDD  
—
—
—
—
—
—
V
V
V
V
0.3 x VDD  
—
0.1 x VDD  
1. Si501 supports OE/mode functionality. Si502 supports OE/mode and FS functionality. Si503 supports only FS functionality. See data  
sheet functional description section for more information.  
2. Frequency stability includes initial tolerance, solder shift, operating temp range, rated power supply voltage change, load change, 10-year  
aging, shock, and vibration.  
3. CL = 15 pF, TR/TF (20% to 80%), 3.3 V unless otherwise stated. See datasheet for additional TR/TF options.  
4. Recommended series termination resistor (RS) = 24.9 for Z0=50 .  
5. Integrated phase jitter exceeds some high-performance data communications system requirements. See AN783 for more information.  
Absolute Maximum Ratings1  
Condition  
Parameter  
Storage Temperature  
Supply Voltage  
Symbol  
Rating  
-55 to 125  
-0.5 to 3.8  
0.5 to VDD +0.3  
2000  
Unit  
ºC  
ºC  
V
TS  
VDD  
Input Voltage  
VIN  
ESD HBM (JESD22-A114)  
ESD CDM  
Solder Temp2  
HBM  
CDM  
TPEAK  
TP  
V
500  
V
260  
ºC  
s
2
Solder Time at TPEAK  
20-40  
Max Junction Temp  
TJ  
125  
ºC  
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not  
implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability.  
2. The device is compliant with JEDEC J-STD-020.  
2
Revision 0.72  
www.silabs.com/cmems  
1234567

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