Datasheet > 5-330808-3

5-330808-3

更新时间： 2024-02-22 13:47:05

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
24页	776K
描述
14-Bit, 80 MSPS/105 MSPS A/D Converter

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技术参数
数据手册

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5-330808-3 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8536.69.40.40	风险等级：	5.71
联系完成配合：	NOT SPECIFIED	触点材料：	NOT SPECIFIED
设备插槽类型：	IC SOCKET	Base Number Matches：	1

5-330808-3 数据手册

AD6645

AD6645ASQ-80/

AD6645ASV-80

AD6645ASQ-105/

AD6645ASV-105

Test

Parameter

Symbol Temp Level Min

Typ

Max

Min

Typ

Max

Unit

DATA-READY (DRY⁴)/DATA(D13:0),, OVR

Data-Ready to DATA Delay (Hold Time)

ꢀ0% Duty Cycle

Data-Ready to DATA Delay (Setup Time) t_{S_DR}

ꢀ0% Duty Cycle

t_{H_DR}

Full

Note ꢀ^ꢀ

7.2

Note ꢀ^ꢀ

ꢀ.7

6.6

2.1

7.9

ꢀ.1

0.6

0.1

6.4

3.ꢀ

Note ꢀ^ꢀ

3.6

2.1

APERTURE DELAY

t_A

t_J

2ꢀ°C

−ꢀ00

0.1

−ꢀ00

APERTURE UNCERTAINTY (JITTER)

ps rms

¹Several timing parameters are a function of t_ENCand t_ENCH

²Several timing parameters are a function of t_ENCLand t_ENCH

³ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, t_{E_RL}= t_{H_E}

⁴DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

^ꢀData-ready to DATA Delay (t_{H_DR}and t_{S_DR}) is calculated relative to rated speed grade and is dependent on t_ENCand duty cycle.

t_A

N + 3

AIN

N + 1

N + 2

t_ENCHt_ENCL

N + 1

N + 4

t_ENC

ENCODE,

ENCODE

N + 2

t_{E_DR}

N + 3

t_{S_E}

t_{E_FL}

t_{E_RL}

t_{H_E}

D[13:0], OVR

DRY

N – 3

N – 2

N – 1

t_{H_DR}

t_{S_DR}

t_DR

Figure 2. Timing Diagram

Rev. D | Page 6 of 24

1...3 4 567 8 9...24

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