4231-52 PDF预览

4231-52

更新时间: 2025-09-12 07:48:03
品牌 Logo 应用领域
PSEMI 开关光电二极管
页数 文件大小 规格书
7页 272K
描述
SPDT High Power UltraCMOS - DC 1.3 GHz RF Switch

4231-52 数据手册

 浏览型号4231-52的Datasheet PDF文件第1页浏览型号4231-52的Datasheet PDF文件第3页浏览型号4231-52的Datasheet PDF文件第4页浏览型号4231-52的Datasheet PDF文件第5页浏览型号4231-52的Datasheet PDF文件第6页浏览型号4231-52的Datasheet PDF文件第7页 
PE4231  
Product Specification  
Figure 3. Pin Configuration (Top View)  
Table 4. DC Electrical Specifications  
Parameter  
Min  
Typ  
Max  
Units  
VDD Power Supply  
Voltage  
2.7  
3.0  
3.3  
V
1
2
3
4
8
7
6
5
VDD  
CTRL  
RF1  
GND  
GND  
RF2  
IDD Power Supply Current  
(VDD = 3V, VCNTL = 3V)  
29  
35  
µA  
4231  
Control Voltage High  
Control Voltage Low  
0.7xVDD  
V
V
GND  
0.3xVDD  
RFCommon  
Table 5. Truth Table  
Table 2. Pin Descriptions  
Control Voltage  
Signal Path  
Pin  
Pin Name  
No.  
Description  
CTRL = CMOS or TTL High  
CTRL = CMOS or TTL Low  
RFCommon to RF1  
RFCommon to RF2  
1
VDD  
Nominal +3 V supply connection.  
2
CTRL  
CMOS or TTL logic level:  
The control logic input pin (CTRL) is typically  
driven by a 3-volt CMOS logic level signal, and  
has a threshold of 50% of VDD. For flexibility to  
support systems that have 5-volt control logic  
drivers, the control logic input has been designed  
to handle a 5-volt logic HIGH signal. (A minimal  
current will be sourced out of the VDD pin when the  
control logic input voltage level exceeds VDD.)  
High = RFCommon to RF1 signal path  
Low = RFCommon to RF2 signal path  
3
GND  
Ground connection. Traces should be  
physically short and connected to ground  
4
5
6
RF Common Common RF port for switch.1  
RF2  
RF2 port.1  
GND  
Ground Connection. Traces should be  
physically short and connected to ground  
Latch-Up Avoidance  
7
8
GND  
RF1  
Ground Connection. Traces should be  
physically short and connected to ground  
Unlike conventional CMOS devices, UltraCMOS™  
devices are immune to latch-up.  
RF1 port.1  
Electrostatic Discharge (ESD) Precautions  
Note 1: All RF pins must be DC blocked with an external  
series capacitor or held at 0 VDC  
.
When handling this UltraCMOS™ device, observe  
the same precautions that you would use with  
other ESD-sensitive devices. Although this device  
contains circuitry to protect it from damage due to  
ESD, precautions should be taken to avoid  
exceeding the rating specified in Table 3.  
Table 3. Absolute Maximum Ratings  
Symbol  
Parameter/  
Conditions  
Min  
Max  
Units  
VDD  
VI  
Power supply voltage  
-0.3  
-0.3  
4.0  
V
V
Voltage on any input ex-  
cept for the CTRL input  
VDD+  
0.3  
VCTRL  
TST  
Voltage on CTRL input  
5.0  
V
Storage temperature  
range  
-65  
-40  
150  
°C  
Operating temperature  
range  
TOP  
PIN  
85  
33  
°C  
dBm  
V
Input power (50)  
ESD voltage (Human  
Body Model)  
VESD  
200  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0097-01 UltraCMOS™ RFIC Solutions  
Page 2 of 7  

与4231-52相关器件

型号 品牌 获取价格 描述 数据表
4231-T110-K0F1H-15A ETA

获取价格

断路器磁性(液力延迟)15A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-10A ETA

获取价格

断路器磁性(液力延迟)10A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-12A ETA

获取价格

额定电流(A):12A;额定直流电压(V):50 V;额定交流电压(V):120 V;断路
4231-T110-K0F2H-15A ETA

获取价格

额定电流(A):15A;额定直流电压(V):50 V;额定交流电压(V):120 V;断路
4231-T110-K0F2H-1A ETA

获取价格

断路器磁性(液力延迟)1A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-2A ETA

获取价格

额定电流(A):2A;额定直流电压(V):50 V;额定交流电压(V):120 V;断路器
4231-T110-K0F2H-3A ETA

获取价格

断路器磁性(液力延迟)3A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-5A ETA

获取价格

断路器磁性(液力延迟)5A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-7A ETA

获取价格

断路器磁性(液力延迟)7A120VAC50VDC按片DIN轨道
4231-T110-K0F2H-8A ETA

获取价格

额定电流(A):8A;额定直流电压(V):50 V;额定交流电压(V):120 V;断路器