Contents
1
Introduction..............................................................................................................9
1.1
Terminology .......................................................................................................9
1.1.1 Processor Packaging Terminology............................................................. 10
References ....................................................................................................... 11
1.2
2
Electrical Specifications........................................................................................... 13
2.1
2.2
Power and Ground Lands.................................................................................... 13
Decoupling Guidelines........................................................................................ 13
2.2.1 Vcc Decoupling ...................................................................................... 13
2.2.2 Vtt Decoupling....................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
Voltage Identification......................................................................................... 14
Market Segment Identification (MSID) ................................................................. 16
Reserved, Unused and TESTHI Signals ................................................................. 16
Voltage and Current Specification........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification........................................................ 19
2.6.3 Vcc Overshoot ....................................................................................... 21
2.6.4 Die Voltage Validation............................................................................. 22
Signaling Specifications...................................................................................... 22
2.7.1 FSB Signal Groups.................................................................................. 23
2.7.2 CMOS and Open Drain Signals ................................................................. 25
2.7.3 Processor DC Specifications ..................................................................... 25
2.7.3.1 GTL+ Front Side Bus Specifications ............................................. 27
Clock Specifications........................................................................................... 28
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................ 28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 29
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 29
2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
PECI DC Specifications....................................................................................... 34
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Package Mechanical Specifications .......................................................................... 35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawing............................................................................... 35
Processor Component Keep-Out Zones................................................................. 39
Package Loading Specifications ........................................................................... 39
Package Handling Guidelines............................................................................... 39
Package Insertion Specifications.......................................................................... 40
Processor Mass Specification............................................................................... 40
Processor Materials............................................................................................ 40
Processor Markings............................................................................................ 40
Processor Land Coordinates................................................................................ 41
4
5
Land Listing and Signal Descriptions ....................................................................... 43
4.1
4.2
Processor Land Assignments............................................................................... 43
Alphabetical Signals Reference............................................................................ 66
Thermal Specifications and Design Considerations .................................................. 75
5.1
Processor Thermal Specifications......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 78
Processor Thermal Features................................................................................ 78
5.2.1 Thermal Monitor..................................................................................... 78
5.2
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