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40002A01 PDF预览

40002A01

更新时间: 2022-09-19 00:08:56
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
12页 197K
描述
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

40002A01 数据手册

 浏览型号40002A01的Datasheet PDF文件第5页浏览型号40002A01的Datasheet PDF文件第6页浏览型号40002A01的Datasheet PDF文件第7页浏览型号40002A01的Datasheet PDF文件第9页浏览型号40002A01的Datasheet PDF文件第10页浏览型号40002A01的Datasheet PDF文件第11页 
ICS840002-01  
FEMTOCLOCKS™ CRYSTAL-TO-  
LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
INPUTS:  
CRYSTAL INPUT:  
OUTPUTS:  
LVCMOS OUTPUT:  
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We  
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.  
Though not required, but for additional protection, a 1kΩ  
resistor can be tied from XTAL_IN to ground.  
TEST_CLK INPUT:  
For applications not requiring the use of the test clock, it can  
be left floating. Though not required, but for additional  
protection, a 1kΩ resistor can be tied from the TEST_CLK to  
ground.  
LVCMOS CONTROL PINS:  
All control pins have internal pull-ups or pull-downs; additional  
resistance is not required but can be added for additional  
protection. A 1kΩ resistor can be used.  
LAYOUT GUIDELINE  
C2=22pF are recommended for frequency accuracy. For differ-  
ent board layout, the C1 and C2 may be slightly adjusted for  
optimizing frequency accuracy. 1KΩ pullup or pulldown resis-  
tors can be used for the logic control input pins.  
Figure 3 shows a schematic example of the ICS840002-01. An  
example of LVCMOS termination is shown in this schematic.  
Additional LVCMOS termination approaches are shown in the  
LVCMOS Termination Application Note. In this example, an 18  
pF parallel resonant 25MHz crystal is used.The C1=22pF and  
Logic Control Input Examples  
Set Logic  
Input to  
'1'  
Set Logic  
Input to  
'0'  
VDD  
VDD  
R2  
33  
Zo = 50 Ohm  
RU1  
1K  
RU2  
Not Install  
VDD  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
U1  
LVCMOS  
RD1  
Not Install  
RD2  
1K  
1
16  
15  
14  
13  
12  
11  
10  
9
FSEL0  
XTAL_SEL  
TEST_CLK  
OE  
MR  
nPLL_SEL  
VDDA  
FSEL1  
GND  
GND  
Q0  
Q1  
VDDO  
XTAL_IN  
XTAL_OUT  
2
3
4
5
6
7
8
VDD  
VDD  
VDDA  
R3  
VDD  
R1  
10  
C3  
10uF  
100  
C4  
0.01u  
C6  
0.1u  
Zo = 50 Ohm  
C5  
0.1u  
ICS840002-01  
R4  
100  
XTAL2  
If not using the crystal input, it can be left floating.  
For additional protection the XTAL_IN pin can be  
tied to ground.  
LVCMOS  
C2  
22pF  
X1  
XTAL1  
Optional Termination  
C1  
22pF  
Unused output can be left floating. There should  
no trace attached to unused output. Device  
characterized with all outputs terminated.  
FIGURE 3. ICS840002-01 SCHEMATIC EXAMPLE  
840002AG-01  
www.icst.com/products/hiperclocks.html  
REV.B JANUARY 13, 2006  
8

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