3D7523-50

更新时间： 2024-01-28 01:27:30

品牌	Logo	应用领域
DATADELAY		解码器网络接口电信集成电路电信电路光电二极管编码器
页数	文件大小	规格书
5页	293K
描述
MONOLITHIC MANCHESTER ENCODER/DECODER

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技术参数
数据手册

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3D7523-50 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.73	JESD-30 代码：	R-PDIP-T14
长度：	19.305 mm	功能数量：	1
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	4.57 mm
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	MANCHESTER ENCODER/DECODER
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

3D7523-50 数据手册

3D7523

APPLICATION NOTES (CONT’D)

DECODER

The Manchester decoder subsystem samples the

input at precise pre-selected intervals to retrieve

the data and to recover the clock from the

received data stream. Its architecture comprises

finely tuned delay elements and proprietary

circuitry which, in conjunction with other circuits,

implement the data decoding and clock recovery

function.

to one over twice the baud rate. Otherwise, the

input is presented at the clock output unchanged,

shifted in time. Therefore, the clock duty cycle is

strongly dependent on the baud rate, as this will

affect the clock-high duration.

The clock output falling edge is not operated on

by the clock recovery circuitry. It, therefore,

preserves more accurately the clock frequency

information embedded in the transmitted data. It

can therefore be used, if desired, to retrieve clock

frequency information.

Typically, the encoded data transmitted from a

source arrives at the decoder corrupted. Such

corruption of the received data manifests itself as

jitter and/or pulse width distortion at the decoder

input. The instantaneous deviations from

nominal Baud Rate and/or Pulse Width (high or

low) adversely impact the data extraction and

clock recovery function if their published limits

are exceeded. See Table 4, Allowed Baud

Rate/Duty Cycle. The decoder, being a self-

timed device, is tolerant of frequency modulation

(jitter) present in the input data stream, provided

that the input data pulse width variations remain

within the allowable ranges.

INPUT SIGNAL CHARACTERISTICS

The 3D7523 inputs are TTL compatible. The

user should assure him/herself that the 1.5

volt TTL threshold is used when referring to all

timing, especially to the input clock duty cycle

(encoder) and the received data (decoder).

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

CMOS integrated circuitry is strongly dependent

on power supply and temperature. The

monolithic 3D7523 Manchester encoder/decoder

utilizes novel and innovative compensation

circuitry to minimize timing variations induced by

fluctuations in power supply and/or temperature.

Nevertheless, optimum performance is achieved

by providing a stable power supply and a clean

ground plane, and by placing a bypass capacitor

(0.1uf typically) as close to the device as

possible.

The decoder presents at its outputs the decoded

data (inverted) and the recovered clock. The

decoded data is valid at the rising edge of the

clock.

The clock recovery function operates in two

modes dictated by the input data stream bit

sequence. When a data bit is succeeded by its

inverse, the clock recovery circuit is engaged and

forces the clock output low for a time equal

ENCODED

RECEIVED

(RX)

t_C

t_CL

t_CWL

t_CD

CLOCK

(CLK)

DATA

(DATB)

DECODED

Figure 2: Timing Diagram (Decoder)

Doc #06003

5/8/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

1 234 5

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3D7523D-25	DATADELAY	MONOLITHIC MANCHESTER ENCODER/DECODER	获取价格
3D7523D-5	DATADELAY	MONOLITHIC MANCHESTER ENCODER/DECODER	获取价格

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