Datasheet > 3D7502D-30

3D7502D-30

更新时间： 2024-02-03 05:18:04

品牌	Logo	应用领域
DATADELAY		电信光电二极管电信集成电路
页数	文件大小	规格书
4页	37K
描述
Manchester Decoder, CMOS, PDSO14, SOIC-14

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技术参数
数据手册

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3D7502D-30 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	14
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.78	JESD-30 代码：	R-PDSO-G14
长度：	8.695 mm	功能数量：	1
端子数量：	14	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大压摆率：	40 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	MANCHESTER DECODER	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	Base Number Matches：	1

3D7502D-30 数据手册

3D7502

APPLICATION NOTES

The 3D7502 Manchester Decoder samples the

input at precise pre-selected intervals to retrieve

the data and to recover the clock from the

received data stream. Its architecture comprises

finely tuned delay elements and proprietary

circuitry which, in conjunction with other circuits,

implement the data decoding and clock recovery

function.

OUTPUT SIGNAL CHARACTERISTICS

The 3D7502 presents at its outputs the decoded

data (inverted) and the recovered clock. The

decoded data is valid at the rising edge of the

clock.

The clock recovery function operates in two

modes dictated by the input data stream bit

sequence. When a data bit is succeeded by its

inverse, the clock recovery circuit is engaged

and forces the clock output low for a time equal

to one over twice the baud rate. Otherwise,

the input is presented at the clock output

unchanged, shifted in time.

INPUT SIGNAL CHARACTERISTICS

Encoded data transmitted from a source arrives

at its destination corrupted. Such corruption of

the received data manifests itself as jitter and/or

pulse width distortion at the input to the device.

The instantaneous deviations from nominal Baud

Rate and/or Pulse Width (high or low) adversely

impact the data extraction and clock recovery

function if their published limits are exceeded.

See Table 4, Allowed Baud Rate/Duty Cycle.

When engaged, the clock recovery circuit

generates a low-going pulse of fixed width.

Therefore, the clock duty cycle is strongly

dependent on the baud rate, as this will affect

the clock-high duration.

The 3D7502 Manchester Decoder Data Input is

TTL compatible. The user should assure

himself that the 1.5 volt TTL threshold is used

when referring to all timing, especially the input

pulse widths.

The clock output falling edge is not operated on

by the clock recovery circuitry. It, therefore,

preserves more accurately the clock frequency

information embedded in the transmitted data.

Therefore, it can be used, if it is desired, to

retrieve clock frequency information.

FREQUENCY (JITTER) ERRORS

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The 3D7502 Manchester Decoder, being a self-

timed device, is tolerant of frequency

modulation (jitter) present in the input data

stream, provided that the input data pulse width

variations remain within the allowable ranges.

CMOS integrated circuitry is strongly dependent

on power supply and temperature. The

monolithic 3D7502 Manchester Decoder utilizes

novel and innovative compensation circuitry to

minimize timing variations induced by

fluctuations in power supply and/or temperature.

ENCODED

RECEIVED

(RX)

t_C

t_CL

t_CWL

t_CD

CLOCK

(CLK)

DATA

(DATB)

DECODED

Figure 1: Timing Diagram

Doc #97032

5/19/97

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

123 4

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与3D7502D-30相关器件

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3D7502D40	ETC	Logic IC	获取价格
3D7502D-40	DATADELAY	Manchester Decoder, CMOS, PDSO14, SOIC-14	获取价格
3D7502D5	ETC	Logic IC	获取价格
3D7502D-5	DATADELAY	Manchester Decoder, CMOS, PDSO14, SOIC-14	获取价格
3D7502D50	ETC	Logic IC	获取价格
3D7502D-50	DATADELAY	Manchester Decoder, CMOS, PDSO14, SOIC-14	获取价格

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