Datasheet > 存储 > OTP ROM> 37LV128-P

37LV128-P

更新时间： 2024-01-04 19:38:34

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管可编程只读存储器 OTP只读存储器电动程控只读存储器时钟
页数	文件大小	规格书
12页	92K
描述
36K, 64K, and 128K Serial EPROM Family

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37LV128-P 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP8,.25
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.91	最大时钟频率 (fCLK)：	10 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.9 mm
内存密度：	131072 bit	内存集成电路类型：	OTP ROM
内存宽度：	32	功能数量：	1
端子数量：	8	字数：	4096 words
字数代码：	4000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4KX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
电源：	3.3/5 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大待机电流：	0.00005 A
子类别：	Other Memory ICs	最大压摆率：	0.01 mA
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.6 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

37LV128-P 数据手册

37LV36/65/128

2.0

DATA

8.0

CASCADING SERIAL EPROMS

Cascading Serial EPROMs provide additional memory

for multiple FPGAs conﬁgured as a daisy-chain, or for

future applications requiring larger conﬁguration mem-

ories.

2.1

Data I/O

Three-state DATA output for reading and input during

programming.

When the last bit from the ﬁrst Serial EPROM is read,

the next clock signal to the Serial EPROM asserts its

CEO output LOW and disables its DATA line. The sec-

ond Serial EPROM recognizes the LOW level on its CE

input and enables its DATA output.

3.0

CLK

3.1

Clock Input

Used to increment the internal address and bit

counters for reading and programming.

When conﬁguration is complete, the address counters

of all cascaded Serial EPROMs are reset if RESET

goes LOW forcing the RESET/OE on each Serial

EPROM to go HIGH. If the address counters are not to

be reset upon completion, then the RESET/OE inputs

can be tied to ground.

4.0

RESET/OE

4.1

Reset Input and Output Enable

A LOW level on both the CE and RESET/OE inputs

enables the data output driver. A HIGH level on

RESET/OE resets both the address and bit counters.

In the 37LVXXX, the logic polarity of this input is pro-

grammable as either RESET/OE or OE/RESET. This

document describes the pin as RESET/OE although

the opposite polarity is also possible. This option is

deﬁned and set at device program time.

Additional logic may be required if cascaded memories

are so large that the rippled chip enable is not fast

enough to activate successive Serial EPROMs.

9.0

STANDBY MODE

The 37LVXXX enters a low-power Standby Mode

whenever CE is HIGH. In Standby Mode, the Serial

EPROM consumes less than 100 µA of current. The

output will remain in a high-impedance state regardless

of the state of the OE input.

5.0

5.1

Chip Enable Input

10.0 PROGRAMMING MODE

CE is used for device selection. A LOW level on both

CE and OE enables the data output driver. A HIGH

level on CE disables both the address and bit counters

and forces the device into a low power mode.

Programming Mode is entered by holding VPP HIGH

(+13 volts) for two clock edges and then holding VPP =

VDD for one clock edge. Programming mode is exited

by driving a LOW on both CE and OE and then remov-

ing power from the device. Figures 4 through 7 show

the programming algorithm.

6.0

CEO

6.1

Chip Enable Output

11.0 37LVXXX RESET POLARITY

This signal is asserted LOW on the clock cycle follow-

ing the last bit read from the memory. It will stay LOW

as long as CE and OE are both LOW. It will then follow

CE until OE goes HIGH. Thereafter, CEO will stay

HIGH until the entire EPROM is read again. This pin

also used to sense the status of RESET polarity when

Programming Mode is entered.

The 37LVXXX lets the user choose the reset polarity as

either RESET/OE or OE/RESET. Any third-party com-

mercial programmer should prompt the user for the

desired reset polarity.

The programming of the overﬂow word should be han-

dled transparently by the EPROM programmer; it is

mentioned here as supplemental information only.

7.0

VPP

The polarity is programmed into the ﬁrst overﬂow word

location, maximum address+1. 00000000 in these

locations makes the reset active LOW, FFFFFFFF in

these locations makes the reset active HIGH. The

default condition is RESET active HIGH.

7.1

Programming Voltage Supply

Used to enter programming mode (+13 volts) and to

program the memory (+13 volts). Must be connected

directly to Vcc for normal Read operation. No over-

shoot above +14 volts is permitted.

1996 Microchip Technology Inc.

DS21109E-page 3

1 234 5 6 7...12

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