Model 357
7x5mm Low Cost
HCMOS/TTL Compatible VCXO
CMOS/TTL OUTPUT WAVEFORM
TEST CIRCUIT, CMOS LOAD
Tr
Tf
VOH
N.C. or Enable Input
+
-
90%, 80%, 2.4V
50%, 1.5V
mA
6
1
5
D.U.T.
2
4
+
+
-
0.01uF
POWER
SUPPLY
VM
C L
10%, 20%, 0.5V
-
capacitance.
3
VOL
UPTIME (t)
PERIOD (T)
-
POWER +
SUPPLY
DUTY CYCLE = t/T x 100 (%)
Enable Input or N.C.
D.U.T. PIN ASSIGNMENTS
PIN
1
SYMBOL
DESCRIPTION
Control Voltage
ENABLE TRUTH TABLE
VC
2
3
4
5
EOH or N.C. Enable or No Connect
PIN 2 or PIN 5
Logic ‘1’
PIN 4
Output
Output
GND
Output
Circuit & Package Ground
RF Output
Open
Logic ‘0’
N.C. or EOH No Connect or Enable
VCC Supply Voltage
High Imp.
6
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
MARKING INFORMATION
(7.0 ±0.2)
0.276 ±0.008
(1.4)
0.055
PIN 1 IDENTIFIER
1. ** - Manufacturing Site Code.
2. YYWW – Date code, YY – year, WW – week.
3. Truncated CTS part number.
4. XXXMXXXX - Frequency marked with 4
significant digits after the ‘M’.
(1.27)
0.050
4
5
2
6
1
CTS ** YYWW
357LB3C
● XXXMXXXX
(5.0 ±0.2)
0.197 ±0.008
(3.73)
0.147
3
NOTES
1. Termination pads (e4), barrier-plating is nickel
(Ni) with gold (Au) flash plate.
2. Reflow conditions per JEDEC J-STD-020.
(2.54)
0.100
(5.08)
0.200
(2.0)
0.079
MAX
(mm)
Inch
Key:
SUGGESTED SOLDER PAD GEOMETRY
SUGGESTED REFLOW PROFILE
.071 [1.80]
300
200
100
0
Maximum 260°C, 10 seconds
Typical 245°C
C BYPASS
6
1
5
4
3
Temp.
(°C)
.165 [4.20]
130°C
.079 [2.00]
2
.100 [2.54]
0
30
60
90
120 150 180 210 240 270 300
[mm]
Key:
Time (Seconds)
.200 [5.08]
Inch
CBYPASS should be ≥ 0.01 uF.
Document No. 008-0244-0
Page 3 - 4
Rev. H
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CTS Electronic Components, Inc. ٠
171 Covington Drive ٠
Bloomingdale, IL 60108 ٠
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