Datasheet > 2N4053

2N4053

更新时间： 2024-02-25 18:28:29

品牌	Logo	应用领域
其他 - ETC		晶体晶体管
页数	文件大小	规格书
20页	1041K
描述
TRANSISTOR \| BJT \| PNP \| 60V V(BR)CEO \| 60A I(C) \| TO-36

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技术参数
数据手册

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2N4053 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.6
最大集电极电流 (IC)：	60 A	配置：	Single
最小直流电流增益 (hFE)：	80	最高工作温度：	125 °C
极性/信道类型：	PNP	最大功率耗散 (Abs)：	170 W
子类别：	Other Transistors	表面贴装：	NO
标称过渡频率 (fT)：	0.002 MHz	Base Number Matches：	1

2N4053 数据手册

CY7C1339

AC Test Loads and Waveforms

R=317

Ω

3.3V

[10]

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

2.5V

GND

90%

10%

=50

Ω

10%

2.5 ns

R =50

Ω

5 pF

R=351

Ω

2.5ns

≤

V = 1.5V

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

[11,12,13]

Switching Characteristics Over the Operating Range

-166

-133

-100

Parameter

Description

Clock Cycle Time

Min.

6.0

1.7

2.0

0.5

Max.

Min.

7.5

1.9

2.5

0.5

Max.

Min.

Max.

Unit

3.5

2.5

0.5

CYC

Clock HIGH

Clock LOW

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-Up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW[3:0] Set-Up Before CLK Rise

BWE, GW, BW[3:0] Hold After CLK Rise

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

3.5

4.0

5.5

1.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

DOH

ADS

ADH

WES

WEH

ADVS

ADVH

Data Input Set-Up Before CLK Rise

Data Input Hold After CLK Rise

Chip Select Set-Up

CES

CEH

CHZ

CLZ

EOHZ

EOLZ

EOV

Chip Select Hold After CLK Rise

[12]

Clock to High-Z

3.5

4.0

3.5

5.5

[12]

Clock to Low-Z

[12, 13]

OE HIGH to Output High-Z

[12, 13]

OE LOW to Output Low-Z

[12]

OE LOW to Output Valid

Notes:

10. Input waveform should have a slew rate of 1 V/ns.

11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (b) of AC test loads.

12. t_CHZ, t_CLZ, t_EOV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mf from steady-state

voltage.

13. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

1...6 7 8910 11 12...20

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