EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Pin configuration and description
2
Pin configuration and description
2.1
Input configuration for PG-DSO-8 package
The pin configuration for all input versions of EiceDRIVER™ 2EDN7534F, 2EDN7434F, 2EDN7533F, 2EDN8534F and
2EDN8533F in the PG-DSO-8 package is shown in Figure 1. Diagrams can be viewed in Chapter 9.2 (PG-DSO-8).
ENA
INA
ENB
OUTA
VDD
1
2
3
4
8
7
6
5
GND
INB
OUTB
Figure 1
Table 3
Pin configuration PG-DSO-8, top view
Pin configuration for PG-DSO-8 package
Symbol Description
Pin
number
1
ENA
Enable input channel A
Logic input. If ENA is high or left open, OUTA is controlled by INA.
ENA low causes OUTA low
2
3
4
5
6
7
8
INA
Input signal channel A
Logic input, controlling OUTA (inverting or non-inverting)
GND
INB
Ground
Gate driver reference ground
Input signal channel B
Logic input, controlling OUTB (inverting or non-inverting)
OUTB
VDD
OUTA
ENB
Driver output channel B
Low-impedance output with source and sink capability
Positive supply voltage
Operating range 4.5 V/8.6 V to 20 V
Driver output channel A
Low-impedance output with source and sink capability
Enable input channel B
Logic Input. If ENB is high or left open, OUTB is controlled by INB.
ENB low causes OUTB low
Datasheet
5
Rev.1.0
2021-10-29