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2EDN8524R PDF预览

2EDN8524R

更新时间: 2024-02-12 05:25:57
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
31页 1082K
描述
Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET and GaN switching

2EDN8524R 数据手册

 浏览型号2EDN8524R的Datasheet PDF文件第2页浏览型号2EDN8524R的Datasheet PDF文件第3页浏览型号2EDN8524R的Datasheet PDF文件第4页浏览型号2EDN8524R的Datasheet PDF文件第6页浏览型号2EDN8524R的Datasheet PDF文件第7页浏览型号2EDN8524R的Datasheet PDF文件第8页 
EiceDRIVER™  
2EDN752x / 2EDN852x  
Product Versions  
1.1  
Undervoltage Lockout Versions  
The two Undervoltage Lockout versions are indicated by the variable x in the product version 2EDNy52x:  
y=7: lower voltage for logic level MOSFETs (4.2 V)  
y=8: higher voltage for standard and superjunction MOSFETs (8.0 V)  
Please refer to the functional description section for more details in Chapter 4 (Undervoltage Lockout (UVLO)).  
1.2  
Logic Versions  
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:  
x=3: inverting input logic  
x=4: non-inverting / direct input logic  
The logic relations between inputs, enable pins and outputs are given in Table 2 for the inverting and non-  
inverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective  
input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage  
lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal.  
Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configurations).  
Table 2  
Logic Table  
Inputs  
Output Inverting  
Output Standard  
ENA  
x
ENB  
x
INA  
INB  
x
UVLO1)  
active  
OUTA  
OUTB  
OUTA  
OUTB  
x
L
L
L
L
L
L
x
x
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
inactive  
L
L
L
L
H
H
L
L
L
H
x
x
H
L
L
L
L
L
x
L
H
L
L
H
H
H
H
H
H
L
L
H
L
L
L
x
H
L
L
L
H
L
H
H
H
H
L
H
L
H
H
L
H
H
L
L
L
H
L
L
H
H
H
L
H
H
L
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.  
Active means that UVLO disable active the output stages.  
1.3  
Package Versions  
The logic and UVLO versions are available in 3 different packages.  
a standard PG-DSO-8-60 (designated by “F”)  
a leadless PG-WSON-8-1 (designated by “G”)  
a small PG-TSSOP-8-1 (designated by “R”)  
Drawings can be viewed in Chapter 8 (Outline Dimensions).  
Data Sheet  
5
Revision2.3  
2016-10-05  

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