Datasheet > 2EDL8014GXUMA1

2EDL8014GXUMA1

更新时间： 2024-01-25 12:46:43

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2EDL8014GXUMA1 数据手册

EiceDRIVER™

2EDL8012/3/4 & 2EDL8112/3/4

Functional Description

Table 2

2EDL811x Truth Table

True differential input comes with inherent shoot through protection by preventing both low and high side to

be on at the same time. It also provides noise immunity against ground bounce. The input stage is designed to

operate reliably against –8/+15 V ground voltage drift. Input logic hysteresis also helps combat disturbances to

the input signal.

3.3

Driver Outputs

The low output impedances allow fast transition of the load transistor. Specifically, the ultra-low impedance

pull down resistances, typically ꢂ.ꢃ Ω for the high side and ꢂ.ꢄꢅ Ω for the low side, keep the gate of the load

transistor down during fast transient events – avoiding dv/dt induced re-turn-on.

3.4

Under Voltage Lockout ꢀUVLOꢁ

The under voltage lockout function ensures that the output can be switched to its high level only if the supply

voltage exceeds the UVLO rising threshold voltage. Thus it can be guaranteed, that the switch transistor is not

switched on if the driving voltage is too low to completely switch on the device, thereby avoiding excessive

power dissipation. The UVLO level is set to a typical value of 7.0 V with 0.5 V hysteresis for supply voltage (V_DD)

and 5.75 V with 0.25 V hysteresis for high side boot voltage (V_HB).

UVLO threshold trigger is synchronous. The clock gating ensures minimum pulse width set by the controller is

obeyed at all times. This increases robustness of the integrated boot diode due to the controllability of the

reserve recovery behavior.

3.5

Minimum Pulse Width

The device responds to input level according to the truth table in section 3.2 as long as the logic signal complies

with the minimum pulse width requirement. Signal pulse longer than the minimum allowable input pulse width

yields valid output. Any output in response to shorter pulses or glitches should be disregarded and filtered out

by the user. Under all allowable operation above input minimum pulse width of 40ns, the output behaves one

to one to the input with minimal pulse width distortion.

100 ns

40 ns

100 ns

TON_IN

Figure 3

Minimum Pulse Width Input-output On-time Transfer Function

Datasheet

Rev. 2.0

2019-05-29

1...3 4 567 8 9...18

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