M29W040
Table 8. Status Register
DQ
Name
Logic Level
Definition
Erase Complete
Note
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Data
Polling
Erase on going
7
DQ
DQ
Program Complete
Program on going
’-1-0-1-0-1-0-1-’ Erase or Program on going
Successive read output complementary
data on DQ6 while Programming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
Program (’0’ on DQ6)
’-0-0-0-0-0-0-0-’
6
Toggle Bit
Error Bit
Complete
Erase or Program
’-1-1-1-1-1-1-1-’
acknowledged.
(’1’ on DQ6) Complete
’1’
’0’
’1’
’0’
’1’
Program or Erase Error
This bit is set to ’1’ if P/E.C. has exceded
the specified time limits.
5
4
Program or Erase on going
Erase Timeout Period Expired P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
Erase
3
Time Bit
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
Erase Timeout Period on
going
’0’
2
1
0
Reserved
Reserved
Reserved
Note:
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand executionwillautomaticallyoutputthosefour
bits. TheP/E.C. automaticallysetsbits DQ3, DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
Instructions and Commands
The Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Power
Down, Block Erase, Chip Erase, Program, Block
Erase Suspend and Erase Resume. Commands
are made of address and data sequences. Ad-
dresses are latched on the falling edge of W or E
and data is latched on the rising of W or E. The
instructions require from 1 to 6 cycles, the first or
first three of which are always write operations
used to initiate thecommand.Theyarefollowed by
either further write cycles to confirm the first com-
mand orexecute the commandimmediately. Com-
mand sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security. Commands are initialised by two preced-
ing codedcycleswhich unlockthe CommandInter-
face.In addition,for Erase,command confirmation
is againpreceeded by the two coded cycles.
Data Polling bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation,it outputsa ’0’. After com-
pletion of the operation,DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at theaddressbeing programmedor at an address
within the block being erased. If the byte to be
programmedbelongsto a protectedblock thecom-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100µs, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
P/E.C. status is indicated during command execu-
tionby DataPolling onDQ7, detectionofToggleon
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