Datasheet > 29104BJA

29104BJA

更新时间： 2024-01-01 23:04:22

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
7页	139K
描述
2K x 8 Asynchronous CMOS Static RAM

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技术参数
数据手册

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29104BJA 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8504.50.80.00
风险等级：	1.32	Is Samacsys：	N
直流电阻：	0.36 Ω	标称电感 (L)：	100 µH
电感器应用：	FILTER CHOKE	电感器类型：	GENERAL PURPOSE INDUCTOR
JESD-609代码：	e3	功能数量：	1
端子数量：	2	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大额定电流：	0.53 A
形状/尺寸说明：	RECTANGULAR PACKAGE	屏蔽：	YES
表面贴装：	YES	端子面层：	Bright Tin (Sn)
端子位置：	DUAL ENDED	端子形状：	WRAPAROUND
测试频率：	0.01 MHz	Base Number Matches：	1

29104BJA 数据手册

HM-65162

Timing Waveforms

(1) TAVAX

(2) TAVQV

ADDRESS

(8) TGHQZ

(5) TGLQV

(7) TEHQZ

(6) TGLQX

(3) TELQV

(9) TAVQX

(4) TELQX

NOTE:

1. W is high for a Read Cycle.

FIGURE 1. READ CYCLE

Addresses must remain stable for the duration of the read is low. To execute consecutive read cycles, E may be tied

cycle. To read, G and E must be ≤ V and W ≥ V . The

IL IH

output buffers can be controlled independently by G while E

low continuously until all desired locations are accessed.

(10) TAVAX

ADDRESS

(14) TWHAX

(11) TELWH

(12) TAVWL

(16) TWLQZ

(13) TWLWH

(20) TWLEH

(19) TWHQX

(21)

TDVEH

(17) TDVWH

(22) TAVWH

(18) TWHDX

NOTE:

1. G is low throughout Write Cycle.

FIGURE 2. WRITE CYCLE I

To write, addresses must be stable, E low and W falling low and input data of the opposite phase to the outputs must not

for a period no shorter than TWLWH. Data in is referenced be applied, (Bus contention). If transitions low

with the rising edge of W, (TDVWH and TWHDX). While simultaneously with the W line transitioning low, or after the

addresses are changing, W must be high. When W falls low, W transition, the output will remain in a high impedance

the I/O pins are still in the output state for a period of TWLQZ state. G is held continuously low.

1 2 3 456 7

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