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29104BJA PDF预览

29104BJA

更新时间: 2024-02-25 14:52:45
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
7页 139K
描述
2K x 8 Asynchronous CMOS Static RAM

29104BJA 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8504.50.80.00
风险等级:1.32Is Samacsys:N
直流电阻:0.36 Ω标称电感 (L):100 µH
电感器应用:FILTER CHOKE电感器类型:GENERAL PURPOSE INDUCTOR
JESD-609代码:e3功能数量:1
端子数量:2最高工作温度:85 °C
最低工作温度:-40 °C最大额定电流:0.53 A
形状/尺寸说明:RECTANGULAR PACKAGE屏蔽:YES
表面贴装:YES端子面层:Bright Tin (Sn)
端子位置:DUAL ENDED端子形状:WRAPAROUND
测试频率:0.01 MHzBase Number Matches:1

29104BJA 数据手册

 浏览型号29104BJA的Datasheet PDF文件第1页浏览型号29104BJA的Datasheet PDF文件第2页浏览型号29104BJA的Datasheet PDF文件第3页浏览型号29104BJA的Datasheet PDF文件第5页浏览型号29104BJA的Datasheet PDF文件第6页浏览型号29104BJA的Datasheet PDF文件第7页 
HM-65162  
o
o
AC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)  
CC  
A
LIMITS  
HM-65162S-9 HM-65162B-9 HM-65162-9  
HM-65162C-9  
SYMBOL  
READ CYCLE  
(1) TAVAX  
(2) TAVQV  
(3) TELQV  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CONDITIONS  
Read Cycle Time  
55  
-
-
70  
-
-
90  
-
-
90  
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3, 4)  
(Notes 1, 3)  
Address Access Time  
55  
55  
70  
70  
90  
90  
90  
90  
Chip Enable Access  
Time  
-
-
-
-
(4) TELQX  
(5) TGLQV  
(6) TGLQX  
(7) TEHQZ  
(8) TGHQZ  
(9) TAVQX  
Chip Enable Output  
Enable Time  
5
-
-
35  
-
5
-
-
50  
-
5
-
-
65  
-
5
-
-
65  
-
ns  
ns  
ns  
ns  
ns  
ns  
(Notes 2, 3)  
(Notes 1, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
(Notes 1, 3)  
Output Enable Access  
Time  
Output Enable Output  
Enable Time  
5
-
5
-
5
-
5
-
Chip Enable Output  
Disable Time  
35  
30  
-
35  
35  
-
50  
40  
-
50  
40  
-
Output Enable Output  
Disable Time  
-
-
-
-
Output Hold From  
Address Change  
5
5
5
5
WRITE CYCLE  
(10) TAVAX  
(11) TELWH  
Write Cycle Time  
55  
45  
-
-
70  
45  
-
-
90  
55  
-
-
90  
55  
-
-
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
Chip Selection to End of  
Write  
(12) TAVWL  
(13) TWLWH  
Address Setup Time  
5
-
-
10  
40  
-
-
10  
55  
-
-
10  
55  
-
-
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
Write Enable Pulse  
Width  
40  
(14) TWHAX  
(15) TGHQZ  
(16) TWLQZ  
Write Enable Read  
Setup Time  
10  
-
-
10  
-
-
10  
-
-
10  
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
Output Enable Output  
Disable Time  
30  
30  
35  
40  
40  
50  
40  
50  
Write Enable Output  
Disable Time  
-
-
-
-
(17) TDVWH  
(18) TWHDX  
(19) TWHQX  
Data Setup Time  
Data Hold Time  
25  
10  
0
-
-
-
30  
10  
0
-
-
-
30  
15  
0
-
-
-
30  
15  
0
-
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
(Notes 1, 3)  
Write Enable Output  
Enable Time  
(20) TWLEH  
(21) TDVEH  
(22) TAVWH  
NOTES:  
Write Enable Pulse  
Setup Time  
45  
25  
45  
-
-
-
40  
30  
50  
-
-
-
55  
30  
65  
-
-
-
55  
30  
65  
-
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
(Notes 1, 3)  
Chip Enable Data  
Setup Time  
Address Valid to End of  
Write  
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate  
equivalent and C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.  
L
L
2. Tested at initial design and after major design changes.  
3. V = 4.5 and 5.5V.  
CC  
4. TAVQV = TELQV + TAVEL.  
4

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