Datasheet > 28F320J5

28F320J5

更新时间： 2022-11-27 09:03:12

品牌	Logo	应用领域
英特尔 - INTEL		存储
页数	文件大小	规格书
53页	638K
描述
StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT

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28F320J5 数据手册

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

are valid. Likewise, the device has a wake time

(t_PHWL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset

and the status register is cleared.

available in 56-lead SSOP (Shrink Small Outline

Package) and µBGA* package (micro Ball Grid

Array). The 32-Mbit is available in 56-lead TSOP

(Thin Small Outline Package), 56-lead SSOP, and

56-bump µBGA packages. Figures 2, 3, and 4

show the pinouts.

The Intel StrataFlash memory devices are

available in several package types. The 64-Mbit is

DQ₀- DQ₁₅

V_CCQ

Output Buffer

Input Buffer

V_CC

Query

I/O Logic

BYTE#

CE₀

CE₁

CE₂

WE#

OE#

RP#

Identifier

Logic

Command

User

Interface

Status

Multiplexer

Data

Comparator

Y-Decoder

X-Decoder

Y-Gating

STS

32-Mbit: A - A₂₁

64-Mbit: A₀⁰_-A₂₂

Input Buffer

Write State

Machine

V_PEN

Program/Erase

Voltage Switch

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Kbyte Blocks

Address

Latch

V_CC

GND

Address

Counter

0606_01

Figure 1. Intel StrataFlash™ Memory Block Diagram

ADVANCE INFORMATION

1...3 4 567 8 9...53

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