Datasheet > 存储 > EEPROM> 28C64A-15/L

28C64A-15/L

更新时间： 2024-02-07 12:58:30

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
10页	132K
描述
64K (8K x 8) CMOS EEPROM

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28C64A-15/L 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCN, LCC32,.45X.55	Reach Compliance Code：	unknown
风险等级：	5.92	最长访问时间：	150 ns
命令用户界面：	NO	数据轮询：	YES
JESD-30 代码：	R-XQCC-N32	JESD-609代码：	e0
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	端子数量：	32
字数：	8192 words	字数代码：	8000
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	8KX8	封装主体材料：	CERAMIC
封装代码：	QCCN	封装等效代码：	LCC32,.45X.55
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	电源：	5 V
认证状态：	Not Qualified	就绪/忙碌：	YES
子类别：	EEPROMs	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	切换位：	NO
最长写入周期时间 (tWC)：	1 ms

28C64A-15/L 数据手册

28C64A

2.4

Write Mode

2.0

DEVICE OPERATION

The Microchip Technology Inc. 28C64A has four basic

modes of operation—read, standby, write inhibit, and

byte write—as outlined in the following table.

The 28C64A has a write cycle similar to that of a Static

RAM. The write cycle is completely self-timed and ini-

tiated by a low going pulse on the WE pin. On the fall-

ing edge of WE, the address information is latched. On

rising edge, the data and the control pins (CE and OE)

are latched. The Ready/Busy pin goes to a logic low

level indicating that the 28C64A is in a write cycle which

signals the microprocessor host that the system bus is

free for other activity. When Ready/Busy goes back to

a high, the 28C64A has completed writing and is ready

to accept another cycle.

Operation

Mode

Rdy/Busy

(1)

CE OE WE

I/O

Read

DOUT

High Z

DIN

Standby

Write Inhibit

Byte Write

Byte Clear

2.5

Data Polling

The 28C64A features Data polling to signal the comple-

tion of a byte write cycle. During a write cycle, an

attempted read of the last byte written results in the

data complement of I/O7 (I/O0 to I/O6 are indetermin-

able). After completion of the write cycle, true data is

available. Data polling allows a simple read/compare

operation to determine the status of the chip eliminating

the need for external hardware.

Automatic Before Each “Write”

Note 1: Open drain output.

2: X = Any TTL level.

2.1

Read Mode

The 28C64A has two control functions, both of which

must be logically satisfied in order to obtain data at the

outputs. Chip enable (CE) is the power control and

should be used for device selection. Output Enable

(OE) is the output control and is used to gate data to the

output pins independent of device selection. Assuming

that addresses are stable, address access time (tACC)

is equal to the delay from CE to output (tCE). Data is

available at the output tOE after the falling edge of OE,

assuming that CE has been low and addresses have

been stable for at least tACC-tOE.

2.6

Electronic Signature for Device

Identification

An extra row of 32 bytes of EEPROM memory is avail-

able to the user for device identification. By raising A9

to 12V ±0.5V and using address locations 1FEO to

1FFF, the additional bytes can be written to or read

from in the same manner as the regular memory array.

2.7

Chip Clear

All data may be cleared to 1's in a chip clear cycle by

raising OE to 12 volts and bringing the WE and CE low.

This procedure clears all data, except for the extra row.

2.2

Standby Mode

The 28C64A is placed in the standby mode by applying

a high signal to the CE input. When in the standby

mode, the outputs are in a high impedance state, inde-

pendent of the OE input.

2.3

Data Protection

In order to ensure data integrity, especially during criti-

cal power-up and power-down transitions, the following

enhanced data protection circuits are incorporated:

First, an internal VCC detect (3.3 volts typical) will inhibit

the initiation of non-volatile programming operation

when VCC is less than the VCC detect circuit trip.

Second, there is a WE filtering circuit that prevents WE

pulses of less than 10 ns duration from initiating a write

cycle.

Third, holding WE or CE high or OE low, inhibits a write

cycle during power-on and power-off (VCC).

DS11109K-page 6

2004 Microchip Technology Inc.

1...3 4 567 8 9 10

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