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251PMI

更新时间： 2024-01-16 12:20:12
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
10页 85K
描述
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

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251PMI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm湿度敏感等级：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：200 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
电源：3.3 V主时钟/晶体标称频率：150 MHz
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Clock Generators最大供电电压：3.45 V
最小供电电压：3.15 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3.9 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

251PMI 数据手册

 浏览型号251PMI的Datasheet PDF文件第1页浏览型号251PMI的Datasheet PDF文件第3页浏览型号251PMI的Datasheet PDF文件第4页浏览型号251PMI的Datasheet PDF文件第5页浏览型号251PMI的Datasheet PDF文件第6页浏览型号251PMI的Datasheet PDF文件第7页 
ICS251 DATASHEET  
Pin Assignment  
Output Clock Selection Table  
S1  
S0  
CLK (MHz)  
Spread  
Percentage  
User  
Configurable  
User  
Configurable  
User  
Configurable  
User  
Configurable  
S 0  
V D D  
1
2
3
4
8
7
6
5
P D T S  
G N D  
User  
Configurable  
User  
Configurable  
User  
Configurable  
User  
Configurable  
0
0
1
1
0
1
0
1
X 1 / I C L K  
X 2  
S 1  
C L K  
8-pin (150 mil) SOIC  
Pin Descriptions  
Pin  
Pin  
Pin  
Pin Description  
Number  
Name  
Type  
1
2
3
4
5
6
7
S0  
VDD  
X1/ICLK  
X2  
Input  
Power  
XI  
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.  
Connect to +3.3 V.  
Connect this pin to a crystal or external clock input.  
Connect this pin to a crystal, or float for clock input.  
XO  
CLK  
S1  
Output Clock output. Weak internal pull-down when tri-state.  
Input  
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.  
Connect this to Ground.  
GND  
Power  
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up  
resistor. The pin must be tied either directly or through the external resistor to  
VDD or GND. External resistor value must be less than 15kOhm.  
8
PDTS  
Input  
External Components  
The ICS251 requires a minimum number of external  
components for proper operation.  
increased in this trimming process, it is important to keep stray  
capacitance to a minimum by using very short PCB traces  
(and no vias) been the crystal and device. Crystal capacitors  
must be connected from each of the pins X1 and X2 to ground.  
Series Termination Resistor  
Clock output traces over one inch should use series  
termination. To series terminate a 50trace (a commonly  
used trace impedance), place a 33resistor in series with the  
clock line, as close to the clock output pin as possible. The  
nominal impedance of the clock output is 20.  
The value (in pF) of these crystal caps should equal (C -6  
L
pF)*2. In this equation, C = crystal load capacitance in pF.  
L
Example: For a crystal with a 16 pF load capacitance, each  
crystal capacitor would be 20 pF [(16-6) x 2] = 20.  
Decoupling Capacitor  
As with any high-performance mixed-signal IC, the ICS251  
must be isolated from system power supply noise to perform  
optimally.  
A decoupling capacitor of 0.01µF must be connected between  
VDD and the PCB ground plane.  
Crystal Load Capacitors  
The device crystal connections should include pads for small  
capacitors from X1 to ground and from X2 to ground. These  
capacitors are used to adjust the stray capacitance of the  
board to match the nominally required crystal load  
capacitance. Because load capacitance can only be  
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER  
2
REVISION E 05/19/14  
1234567...10

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