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2510CG-T PDF预览

2510CG-T

更新时间: 2024-01-31 04:36:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 81K
描述
PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24

2510CG-T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.06系列:2510
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

2510CG-T 数据手册

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ICS2510C  
Electrical Characteristics - Input & Supply  
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)  
PARAMETER  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
Operating current  
Input Capacitance  
Output Capacitance  
SYMBOL  
VIH  
CONDITIONS  
MIN  
2
TYP  
MAX  
VDD + 0.3  
0.8  
UNITS  
V
VIL  
VSS - 0.3  
V
IIH  
VIN = VDD  
VIN = 0 V;  
0.1  
19  
140  
4
100  
uA  
uA  
mA  
pF  
IIL  
50  
IDD1  
CL = 0 pF; FIN @ 66M  
Logic Inputs  
170  
1
CIN  
1
CO  
Logic Outputs  
8
pF  
1Guaranteed by design, not 100% tested in production.  
Timing requirements over recommended ranges of supply  
voltage and operating free-air temperature  
Symbol Parameter  
Test Conditions  
Min.  
Max.  
Unit  
Input clock  
frequency  
Fclk  
25  
175  
MHz  
Input clock  
frequency duty  
cycle  
Stabilization time  
40  
60  
1
%
After power up  
ms  
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its  
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal  
Until phase lock is obtained, the specifications for parameters given in the switching  
0010G09/22/09  
4

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