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24LC41A

更新时间： 2024-02-07 23:25:40

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
18页	234K
描述
1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial EEPROM

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24LC41A 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP8,.3	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.84
Is Samacsys：	N	其他特性：	ALSO CONTAINS 128 X 8 BIT MEMORY BLOCK
最大时钟频率 (fCLK)：	0.4 MHz	数据保留时间-最小值：	40
耐久性：	10000000 Write/Erase Cycles	I2C控制字节：	1010XXMR/1010XXXR
JESD-30 代码：	R-PDIP-T8	长度：	9.46 mm
内存密度：	4096 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端口数量：	2	端子数量：	8
字数：	512 words	字数代码：	512
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	4.32 mm	串行总线类型：	I2C
最大待机电流：	0.00006 A	子类别：	EEPROMs
最大压摆率：	0.003 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V	标称供电电压 (Vsup)：	3 V
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	最长写入周期时间 (tWC)：	10 ms
写保护：	HARDWARE	Base Number Matches：	1

24LC41A 数据手册

24LC41A

3.5

Acknowledge

3.0

BIDIRECTIONAL BUS

CHARACTERISTICS

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Characteristics for the Bidirectional bus are identical for

both the DDC Monitor Port (in Bidirectional mode) and

the Microcontroller Access Port The following bus pro-

tocol has been defined:

Note:

The microcontroller access port and the

DDC Monitor Port (in Bidirectional mode)

will not generate any Acknowledge bits if

an internal programming cycle is in

progress.

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

The device that acknowledges has to pull down the

DSDA or MSDA line during the Acknowledge clock

pulse in such a way that the DSDA or MSDA line is

stable low during the high period of the acknowledge

related clock pulse. Of course, setup and hold times

must be taken into account. A master must signal an

end of data to the slave by not generating an Acknowl-

edge bit on the last byte that has been clocked out of

the slave. In this case, the slave must leave the data

line high to enable the master to generate the Stop

condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line

while the clock (DSCL or MSCL) is high determines a

Start condition. All commands must be preceded by a

Start condition.

3.6

Device Addressing

A control byte is the first byte received following the

Start condition from the master device. The first part of

the control byte consists of a 4-bit control code. This

control code is set as 1010 for both read and write

operations and is the same for both the DDC Monitor

Port and Microcontroller Access Port. The next three

bits of the control byte are block select bits (B1, B2, and

B0). All three of these bits are zero for the DDC Monitor

Port. The B2 and B1 bits are don’t care bits for the

Microcontroller Access Port, and the B0 bit is used by

the Microcontroller Access Port to select which of the

two 256 word blocks of memory are to be accessed

(see Figure 3-4). The B0 bit is effectively the Most

Significant bit of the word address. The last bit of the

control byte defines the operation to be performed.

When set to one, a read operation is selected; when set

to zero, a write operation is selected. Following the Start

condition, the device monitors the DSDA or MSDA bus

checking the device type identifier being transmitted,

upon a 1010 code the slave device outputs an Acknowl-

edge signal on the SDA line. Depending on the state of

the R/W bit, the device will select a read or a write

operation. The DDC Monitor Port and Microcontroller

Access Port can be accessed simultaneously because

they are completely independent of one another.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line

while the clock (DSCL or MSCL) is high determines a

Stop condition. All operations must be ended with a

Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last eight will

be stored when doing a write operation. When an over-

write does occur, it will replace data in a first in first out

fashion.

Operation Control Code Block Select R/W

Read

Write

1010

B2B1B0

 2003 Microchip Technology Inc.

DS21176D-page 7

1...4 5 678 9 10...18

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