5秒后页面跳转
24LC41A PDF预览

24LC41A

更新时间: 2024-01-23 04:40:00
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 234K
描述
1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial EEPROM

24LC41A 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP8,.3针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.84
Is Samacsys:N其他特性:ALSO CONTAINS 128 X 8 BIT MEMORY BLOCK
最大时钟频率 (fCLK):0.4 MHz数据保留时间-最小值:40
耐久性:10000000 Write/Erase CyclesI2C控制字节:1010XXMR/1010XXXR
JESD-30 代码:R-PDIP-T8长度:9.46 mm
内存密度:4096 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端口数量:2端子数量:8
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512X8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
电源:3/5 V认证状态:Not Qualified
座面最大高度:4.32 mm串行总线类型:I2C
最大待机电流:0.00006 A子类别:EEPROMs
最大压摆率:0.003 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mm最长写入周期时间 (tWC):10 ms
写保护:HARDWAREBase Number Matches:1

24LC41A 数据手册

 浏览型号24LC41A的Datasheet PDF文件第3页浏览型号24LC41A的Datasheet PDF文件第4页浏览型号24LC41A的Datasheet PDF文件第5页浏览型号24LC41A的Datasheet PDF文件第7页浏览型号24LC41A的Datasheet PDF文件第8页浏览型号24LC41A的Datasheet PDF文件第9页 
24LC41A  
FIGURE 2-5:  
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA  
The 24LC41A was designed to comply to the  
portion of flowchart inside dash box.  
Display Power-on  
or  
DDC Circuit Powered  
from +5 volts  
Communication  
is idle  
Is Vsync  
present?  
No  
Yes  
No  
High-to-low  
transition on  
SCL?  
Send EDID continuously  
using Vsync as clock  
Yes  
High-to-low  
transition on  
SCL?  
No  
Yes  
Stop sending EDID.  
DDC2 communication  
idle. Display waiting for  
address byte.  
Switch to DDC2 mode.  
Display has  
optional  
No  
transition state  
DDC2B  
address  
received?  
Yes  
?
Yes  
Receive DDC2B  
command  
Set Vsync counter = 0  
or start timer  
No  
Reset counter or timer  
Respond to DDC2B  
command  
Change on  
SCL, SDA or  
VCLK lines?  
No  
Yes  
Is display  
Access.bus  
capable?  
No  
TM  
High - low  
transition on SCL  
No  
?
Yes  
Yes  
Reset Vsync counter = 0  
No  
Valid Access.bus  
address?  
Valid  
DDC2 address  
received?  
Yes  
Yes  
No  
No  
See Access.bus  
specification to determine  
correct procedure.  
VCLK  
cycle?  
Yes  
Increment VCLK counter  
(if appropriate)  
No  
Counter=128 or  
timer expired?  
Yes  
Switch back to DDC1  
mode.  
Note 1: The base flowchart is copyright 1993, 1994, 1995 Video Electronic Standard Association (VESA) from  
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.  
2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.  
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.  
DS21176D-page 6  
2003 Microchip Technology Inc.  

与24LC41A相关器件

型号 品牌 描述 获取价格 数据表
24LC41A/P MICROCHIP 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8

获取价格

24LC41A-/P MICROCHIP 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial E

获取价格

24LC41A-I/P MICROCHIP 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial E

获取价格

24LC41I/P MICROCHIP 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8

获取价格

24LC41-I/P ETC I2C Serial EEPROM

获取价格

24LC41IP MICROCHIP 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial E

获取价格