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24LC1025T-E/P

更新时间： 2024-02-09 09:44:18

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
22页	351K
描述
1024K I2C⑩ CMOS Serial EEPROM

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24LC1025T-E/P 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	Factory Lead Time：	10 weeks
风险等级：	1.29	其他特性：	200 YEARS DATA RETENTION
最大时钟频率 (fCLK)：	0.4 MHz	数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles	I2C控制字节：	1010MDDR
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	内存密度：	1048576 bit
内存集成电路类型：	EEPROM	内存宽度：	8
湿度敏感等级：	3	功能数量：	1
端子数量：	8	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	260
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	串行总线类型：	I2C
最大待机电流：	0.000005 A	子类别：	EEPROMs
最大压摆率：	0.005 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm	最长写入周期时间 (tWC)：	5 ms
写保护：	HARDWARE	Base Number Matches：	1

24LC1025T-E/P 数据手册

24AA1025/24LC1025/24FC1025

FIGURE 5-1:

CONTROL BYTE

FORMAT

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code; for the

24XX1025, this is set as ‘1010’ binary for read and

write operations. The next bit of the control byte is the

block select bit (B0). This bit acts as the A16 address

bit for accessing the entire array. The next two bits of

the control byte are the Chip Select bits (A1, A0). The

Chip Select bits allow the use of up to four 24XX1025

devices on the same bus and are used to select which

device is accessed. The Chip Select bits in the control

byte must correspond to the logic levels on the corre-

sponding A1 and A0 pins for the device to respond.

These bits are in effect the two Most Significant bits of

the word address.

Read/Write Bit

Block

Select

Bits

Chip

Select

Bits

Control Code

B0 A1 A0 R/W ACK

Slave Address

Start Bit

Acknowledge Bit

5.1

Contiguous Addressing Across

Multiple Devices

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected, and when set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). The upper

address bits are transferred first, followed by the Less

Significant bits.

The Chip Select bits A1, A0 can be used to expand the

contiguous address space for up to 4 Mbit by adding up

to four 24XX1025’s on the same bus. In this case,

software can use A0 of the control byte as address bit

A16 and A1 as address bit A17. It is not possible to

sequentially read across device boundaries.

Each device has internal addressing boundary

limitations. This divides each part into two segments of

512K bits. The block select bit ‘B0’ controls access to

each “half”.

Following the Start condition, the 24XX1025 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a ‘1010’ code and appro-

priate device select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX1025 will select a read or

write operation.

Sequential read operations are limited to 512K blocks.

To read through four devices on the same bus, eight

random Read commands must be given.

This device has an internal addressing boundary

limitation that is divided into two segments of 512K bits.

Block select bit ‘B0’ to control access to each segment.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte

Address High Byte

Address Low Byte

•

R/W

12 11

15 14 13

Block

Select

Bit

Chip

Select

Bits

Control

Code

X = “don’t care” bit

Preliminary

DS21941E-page 7

1...4 5 678 9 10...22

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