Datasheet > 存储 > EEPROM> 24LC1025-E/SN

24LC1025-E/SN

更新时间： 2024-02-28 07:33:26

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
26页	296K
描述
1024K I2C™ CMOS Serial EEPROM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

24LC1025-E/SN 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	Factory Lead Time：	10 weeks
风险等级：	1.29	其他特性：	200 YEARS DATA RETENTION
最大时钟频率 (fCLK)：	0.4 MHz	数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles	I2C控制字节：	1010MDDR
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	内存密度：	1048576 bit
内存集成电路类型：	EEPROM	内存宽度：	8
湿度敏感等级：	3	功能数量：	1
端子数量：	8	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	260
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	串行总线类型：	I2C
最大待机电流：	0.000005 A	子类别：	EEPROMs
最大压摆率：	0.005 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm	最长写入周期时间 (tWC)：	5 ms
写保护：	HARDWARE	Base Number Matches：	1

24LC1025-E/SN 数据手册

24AA1025/24LC1025/24FC1025

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

4.5

Acknowledge

Accordingly, the following bus conditions have been

defined (Figure 4-1).

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

4.1

Bus Not Busy (A)

Both data and clock lines remain high.

Note:

The 24XX1025 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress, however, the

control byte that is being polled must

match the control byte used to initiate the

write cycle.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

A device that acknowledges must pull-down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX1025) will leave the data line high to enable

the master to generate the Stop condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

To Change

Stop

Condition

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

SCL

SDA

Data from transmitter

The transmitter must release the SDA line at this

point allowing the receiver to pull the SDA line low

to acknowledge the previous eight bits of data.

The receiver must release the SDA line at this

point so the transmitter can continue sending

data.

 2010 Microchip Technology Inc.

DS21941G-page 7

1...4 5 678 9 10...26

下载PDF

与24LC1025-E/SN相关器件

型号	品牌	描述	获取价格	数据表
24LC1025-I/P	MICROCHIP	1024K I2C⑩ CMOS Serial EEPROM	获取价格
24LC1025-I/SM	MICROCHIP	1024K I2C⑩ CMOS Serial EEPROM	获取价格
24LC1025-I/SN	MICROCHIP	1024K I2C™ CMOS Serial EEPROM	获取价格
24LC1025-IP	MICROCHIP	1024K I2Câ¢ Serial EEPROM	获取价格
24LC1025-I-SM	MICROCHIP	1024K I2Câ¢ Serial EEPROM	获取价格
24LC1025T	MICROCHIP	1024K I2C™ CMOS Serial EEPROM	获取价格

与24LC1025-E/SN相关文章

深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

4
74HC573三态非易失锁存器(Latch)资料手册参数分析
2024-05-10

3
MAX3232 RS-232电平转换器资料手册参数分析
2024-05-10

4
MAX485 RS-485/RS-422收发器资料手册参数分析
2024-05-10

4

产品中心

服务支持

精选活动

关于我们

帮助中心

24LC1025-E/SN

24LC1025-E/SN 技术参数

24LC1025-E/SN 数据手册

与24LC1025-E/SN相关器件

与24LC1025-E/SN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

24LC1025-E/SN

24LC1025-E/SN 技术参数

24LC1025-E/SN 数据手册

与24LC1025-E/SN相关器件

与24LC1025-E/SN相关文章

您还可以找

您在本页遇到什么问题？