24AA1025/24LC1025/24FC1025
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Clock frequency
Min.
Max.
Units
Conditions
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V (Note 5)
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
1
2
3
4
FCLK
THIGH
TLOW
TR
—
—
—
100
400
1000
kHz
Clock high time
Clock low time
4000
600
500
—
—
—
ns
ns
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
4700
1300
500
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
5
6
TF
SDA and SCL fall time
(Note 1)
—
—
300
100
ns
ns
All except, 24FC1025
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
THD:STA Start condition hold time
4000
600
250
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
7
TSU:STA Start condition setup time
4700
600
250
—
—
—
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
8
9
THD:DAT Data input hold time
TSU:DAT Data input setup time
0
—
ns
ns
(Note 2)
250
100
100
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
10
11
12
13
14
15
16
TSU:STO Stop condition setup time
TSU:WP WP setup time
4000
600
250
—
—
—
ns
ns
ns
ns
ns
ns
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
4000
600
600
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
THD:WP WP hold time
4700
1300
1300
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
TAA
Output valid from clock
—
—
—
3500
900
400
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
(Note 2)
TBUF
TOF
TSP
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB
250
250
All except, 24FC1025 (Note 1)
24FC1025 (Note 1)
Input filter spike suppression
(SDA and SCL pins)
—
50
All except, 24FC1025 (Notes 1 and 3)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 3
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