Datasheet > 24C16B-I/P

24C16B-I/P

更新时间： 2024-01-03 10:25:23

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
13页	118K
描述
2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8

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24C16B-I/P 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	0.300 INCH, PLASTIC, DIP-8	针数：	8
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.89
Is Samacsys：	N	其他特性：	2-WIRE SERIAL INTERFACE; DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED
最大时钟频率 (fCLK)：	0.1 MHz	数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles	I2C控制字节：	1010MMMR
JESD-30 代码：	R-PDIP-T8	JESD-609代码：	e0
长度：	9.46 mm	内存密度：	16384 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	2048 words	字数代码：	2000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	4.32 mm
串行总线类型：	I2C	最大待机电流：	0.0001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
最长写入周期时间 (tWC)：	10 ms	写保护：	HARDWARE
Base Number Matches：	1

24C16B-I/P 数据手册

24C08B/16B

5.0

ACKNOWLEDGE POLLING

7.0

READ OPERATION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately.This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random

read, and sequential read.

7.1

Current Address Read

The 24C08B/16B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one, the

24C08B/16B issues an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer but does generate a stop condition and the

24C08B/16B discontinues transmission (Figure 7-1).

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

7.2

Random Read

Send Stop

Condition to

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set.This is done by sending the word address to the

24C08B/16B as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24C08B/16B will then

issue an acknowledge and transmits the 8-bit data

word. The master will not acknowledge the transfer but

does generate a stop condition and the 24C08B/16B

discontinues transmission (Figure 7-2).

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

7.3

Sequential Read

(ACK = 0)?

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24C08B/16B transmits

the ﬁrst data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24C08B/16B to transmit the next sequen-

tially addressed 8 bit word (Figure 7-3).

YES

Operation

To provide sequential reads the 24C08B/16B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when

the WP pin is connected to VCC. Programming will be

inhibited and the entire memory will be write-protected.

7.4

Noise Protection

The 24C08B/16B employs aVCC threshold detector cir-

cuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

1999 Microchip Technology Inc.

DS21081F-page 7

1...4 5 678 9 10...13

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