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24C16B-EP PDF预览

24C16B-EP

更新时间: 2024-01-28 15:53:13
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 78K
描述
8K/16K 5.0V I 2 C O Serial EEPROMs

24C16B-EP 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.65
数据保留时间-最小值:10耐久性:10000 Write/Erase Cycles
I2C控制字节:1010MMMRJESD-30 代码:R-PDIP-T8
JESD-609代码:e0内存密度:16384 bit
内存集成电路类型:EEPROM内存宽度:8
端子数量:8字数:2048 words
字数代码:2000最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
电源:5 V认证状态:Not Qualified
串行总线类型:I2C最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.003 mA
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
写保护:HARDWAREBase Number Matches:1

24C16B-EP 数据手册

 浏览型号24C16B-EP的Datasheet PDF文件第1页浏览型号24C16B-EP的Datasheet PDF文件第2页浏览型号24C16B-EP的Datasheet PDF文件第4页浏览型号24C16B-EP的Datasheet PDF文件第5页浏览型号24C16B-EP的Datasheet PDF文件第6页浏览型号24C16B-EP的Datasheet PDF文件第7页 
24C08B/16B  
TABLE 1-3:  
AC CHARACTERISTICS  
Parameter  
Symbol  
Min  
Max  
Units  
Remarks  
Clock frequency  
FCLK  
THIGH  
TLOW  
TR  
4000  
4700  
100  
kHz  
ns  
Clock high time  
Clock low time  
ns  
SDA and SCL rise time  
SDA and SCL fall time  
START condition hold time  
1000  
300  
ns  
(Note1)  
(Note 1)  
TF  
ns  
THD:STA  
4000  
ns  
After this period the first clock  
pulse is generated  
START condition setup time  
TSU:STA  
4700  
ns  
Only relevant for repeated  
START condition  
Data input hold time  
Data input setup time  
STOP condition setup time  
Output valid from clock  
Bus free time  
THD:DAT  
TSU:DAT  
TSU:STO  
TAA  
0
ns  
ns  
ns  
ns  
ns  
250  
4000  
3500  
(Note 2)  
TBUF  
4700  
Time the bus must be free before  
a new transmission can start  
Output fall time from VIH  
min to VIL max  
TOF  
TSP  
TWR  
250  
50  
ns  
ns  
(Note 1), CB 100 pF  
Input filter spike suppres-  
sion (SDA and SCL pins)  
(Note 3)  
Write cycle time  
10  
ms  
Byte or Page mode  
Endurance  
24C08B  
24C16B  
1M  
10M  
cycles  
25°C, VCC = 5.0V, Block Mode  
(Note 4)  
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.  
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.  
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved  
noise and spike suppression. This eliminates the need for a TI specification.  
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-  
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.  
FIGURE 1-2: BUS TIMING DATA  
TR  
TF  
THIGH  
TLOW  
SCL  
TSU:STA  
THD:DAT  
TSU:DAT  
TSU:STO  
THD:STA  
SDA  
IN  
TSP  
TBUF  
TAA  
TAA  
THD:STA  
SDA  
OUT  
1996 Microchip Technology Inc.  
DS21081D-page 3  

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