Datasheet > 21281-DA

21281-DA

更新时间： 2024-01-02 01:36:37

品牌	Logo	应用领域
英特尔 - INTEL		时钟外围集成电路
页数	文件大小	规格书
4页	135K
描述
RISC Microprocessor, 32-Bit, 166MHz, CMOS, PQFP144, TQFP-144

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21281-DA 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP144,.87SQ,20
针数：	144	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.3	HTS代码：	8542.31.00.01
风险等级：	5.92	地址总线宽度：	32
位大小：	32	边界扫描：	YES
最大时钟频率：	166 MHz	外部数据总线宽度：	32
格式：	FIXED POINT	集成缓存：	NO
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
长度：	20 mm	低功率模式：	YES
端子数量：	144	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP144,.87SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.7 mm
速度：	166 MHz	子类别：	Microprocessors
最大供电电压：	2.2 V	最小供电电压：	1.8 V
标称供电电压：	2 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	20 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

21281-DA 数据手册

Memory-Management Units

The instruction set has eight instruction

classes:

is round-robin within a set. The Icache can

be enabled or disabled independent of the

memory-management function. When

memory management is disabled, the

Icache control logic considers all memory

to be cacheable.

The SA-110 has two MMUs: instruction

(IMMU) and data (DMMU). Separate

translation lookaside buffers (TLBs) are

implemented for the instruction and data

streams. The TLBs each have 32 entries

that can each map a segment, a large page,

or a small page. The TLB entry

• Two instruction classes use the onchip

ALU, barrel shifter, and multiplier to

perform high-speed operations on the

data in a bank of 16 logical (31 physical)

32-bit registers.

Data Cache

The write-back Dcache supports the flush-

all-entry, flush-entry, and copyback-entry

functions. The copyback-all function is

not provided in hardware but can be

provided by software. The Dcache entries

are allocated with read transactions and

the entry replacement logic uses a round-

robin algorithm.

• Three instruction classes control data

transfer between memory and the

registers. The classes are optimized for

flexible addressing, rapid context

switching, and swapping data.

replacement algorithm is round-robin. The

data TLB supports both the flush-all and

the flush-single-entry function, while the

instruction TLB supports only the flush-

all function. Memory-management

exceptions preserve the base address

registers, eliminating the need for “fix-up”

code.

• Two instruction classes control

execution flow and execution privilege

level.

Clocks

• One instruction class accesses the

privileged state of the SA-110.

Cache

The SA-110 receives a 3.68-MHz clock

from a crystal-based clock generator. The

SA-110 uses an internal PLL to multiply

the frequency by a variable multiplier to

produce a high-speed clock. The high-

speed clock is then divided internally by a

configurable ratio to provide a system

clock for synchronous operation. The

3.68-MHz oscillator and PLL run

constantly in normal and idle mode.

The SA-110 has a 16KB, 32-way, set-

associative Icache with 32-byte blocks

and a 16KB, 32-way, set-associative,

write-back Dcache with 32-byte blocks.

The core logic implements 32-bit virtual

addresses and 32-bit physical addresses. A

12-bit multiplier with early termination

performs multiplication. The number of

cycles needed to perform a multiplication

operation depends on the magnitude of the

operands, as shown in Table 1.

Instruction Cache

The Icache supports the flush-all-entry

function, and the replacement algorithm

Boundary-Scan Test Logic

Core Logic Multiplication Functions

The SA-110 boundary-scan interface

provides for driving and sampling of all

the external pins of the device except

npwrslp, irrespective of the core logic

state. This ability permits testing of:

Multiplication Operation

(Signed or Unsigned)

Result

Size

Operation

Duration

32 x 32

32 x 32 + 32

32 x 32

32 bits

64 bits

2–4 cycles

3–5 cycles

• SA-110 electrical connections to the

circuit board.

32 x 32 + 64

• Integrity of connections between

devices having a similar interface on the

circuit board.

Signal Lines

Figure 2 shows the signal connects to and

from the SA-110. The signals are arranged

within functional groups.

21 May 1997

1 234

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与21281-DA相关器件

型号	品牌	描述	获取价格	数据表
21281DB	INTEL	IntelÂ® StrongARMÂ® SA-110 Microprocessor	获取价格
21281-DB	INTEL	暂无描述	获取价格
21281EB	INTEL	IntelÂ® StrongARMÂ® SA-110 Microprocessor	获取价格
21281-EB	INTEL	RISC Microprocessor, 32-Bit, 233MHz, CMOS, PQFP144, TQFP-144	获取价格
21281FB	INTEL	IntelÂ® StrongARMÂ® SA-110 Microprocessor	获取价格
21285	INTEL	Microprocessor	获取价格

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