SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
ODD/
EVEN
I
Port-A parity-error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low. Bytes are organized as
A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of the ODD/EVEN input.
O
PEFA
PEFB
(port A) TheparitytreesusedtochecktheA0–A35inputsaresharedbythemail2registertogenerateparityifparitygeneration
is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA high, and PGA
high, the PEFA flag is forced high, regardless of the state of the A0–A35 inputs.
Port-Bparity-error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes areorganized
as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state
O
of the ODD/EVEN input.
(port B)
TheparitytreesusedtochecktheB0–B35inputsaresharedbythemail1registertogenerateparityifparitygeneration
is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1 and SIZ0 high,
and PGB high, the PEFB flag is forced high, regardless of the state of the B0–B35 inputs.
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGA
PGB
I
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.
The generated parity bits are output in the most-significant bit of each byte.
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. This sets the AFA, AFB, MBF1, and MBF2 flags high and the EFA, EFB, AEA, AEB, FFA, and FFB
flags low. The low-to-high transition of RST latches the status of the FS1 and FS0 inputs to select AF flag and AE flag
offset.
RST
I
Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following
low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.
I
SIZ0, SIZ1
SW0, SW1
(port B)
Port-B byte-swap selects. At the beginning of each long word transfer, one of four modes of byte-order swapping is
selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
I
(port B)
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RA
W/RB
I
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is high.
detailed description
reset
The SN74ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loadsthealmost-fullandalmost-emptyoffsetregister(X)withthevalueselected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
