Datasheet > 1N4148WS

1N4148WS

更新时间： 2024-02-21 06:24:45

品牌	Logo	应用领域
德州仪器 - TI		二极管光电二极管
页数	文件大小	规格书
9页	324K
描述
TPS7A1601EVM-046

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技术参数
数据手册

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1N4148WS 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8541.10.00.70	风险等级：	5.76
配置：	SINGLE	二极管类型：	RECTIFIER DIODE
最大正向电压 (VF)：	0.715 V	最大非重复峰值正向电流：	2 A
元件数量：	1	最高工作温度：	150 °C
最大输出电流：	0.15 A	最大重复峰值反向电压：	75 V
最大反向恢复时间：	0.004 µs	子类别：	Rectifier Diodes
表面贴装：	YES	Base Number Matches：	1

1N4148WS 数据手册

www.ti.com

Board Layout

Where T_Jis the junction temperature, T_Ais the ambient temperature, P_Dis the power dissipation in the

device (W), and θ_JAis the thermal resistance from junction to ambient. All temperatures are in degrees

Celsius. The maximum silicon junction temperature, T_J, must not be allowed to exceed 150°C. The layout

design must use copper trace and plane areas effectively, as thermal sinks, in order not to allow T_Jto

exceed the absolute maximum rating under all temperature conditions and voltage conditions across the

part.

The designer must consider carefully the thermal design of the PCB for optimal performance over

temperature. For this EVM, Figure 5 shows that the PCB top GND plane has six, 6-mil, thermal via

connections to the bottom-side copper GND plane to dissipate heat. The PCB is a two-layer board with

2-oz. copper on top and bottom layers. The DGN package drawing can be found at the Texas Instruments

Web site in the product folder for the TPS7A16xx LDO linear regulator.

Table 1 repeats information from the Dissipation Ratings Table of the TPS7A16xx data sheet for

comparison with the thermal resistance, θ_JA, calculated for this EVM layout to show the wide variation in

thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC

High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and

2-oz copper traces on top and bottom of the board.

Table 1. Thermal Resistance, θ_JA, and Maximum Power Dissipation

Max Dissipation without Derating Max Dissipation without Derating

Board

Package

θ_JA

(T_A= 25°C)

(T_A= 70°C)

998 mW

1.41.W

High-K

DGN

55.09°C/W

38.89°C/W

1.8 mW

TPS7A1601EVM-046

2.57 W

The thermal resistance for the TPS7A1601EVM-046, θ_JA, is the measured value for this particular layout

scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the

package.

Board Layout

Figure 4. Top-Layer Silkscreen

SLVU549–December 2011

TPS7A1601EVM-046

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