Datasheet > 1894-40

1894-40

更新时间： 2023-12-26 08:59:41

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
54页	570K
描述
10Base-T/100Base-TX Integrated PHYceiver? with RMII Interface

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

1894-40 数据手册

ICS1894-40

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

PHYCEIVER

Number

Name

Type

Pin Description

SPEED/

TXCLK

IO/Ipu 10M/100M select as input (during power on reset and hardware reset)

Transmit clock as output in MII mode

TXEN

TXD0

Input Transmit enable for both RMII and MII modes

Input Transmit data Bit 0 for both RMII and MII modes

Power Core Power Supply

VDDD

LED3

IO/Ipu LED3 output

TXD1

Input Transmit data Bit 1for both RMII and MII modes

Input Transmit data Bit 2 for MII mode

Input Transmit data Bit 3 for MII mode

Output 25 MHz crystal output

TXT2

TXD3

REF_OUT

REF_IN

P4/LED2

Input 25 MHz crystal (or clock) input for MII mode. 50MHz clock input for RMII mode

IO/Ipu PHY address Bit 4 as input (always latched high during power on reset and

hardware reset) and LED # 2 as output

P0/LED0

PHY address Bit 0 as input (during power on reset and hardware reset) and LED #

0(function configurable, default is "activity/no activity") as output

P1/ISO/LED1

PHY address Bit 1 as input (during power on reset and hardware reset) and LED #

1 (function configurable, default is "10/100 mode") as output

Notes:

1. AIO: Analog input/output PAD.

IO: Digital input/output.

IN/Ipu: Digital input with internal 20k pull-up.

IN/Ipd: Digital input with internal 20k pull-down.

IO/Ipu: Digital input/output with internal 20k pull-up.

IO/Ipd: Digital input/output with internal 20k pull-down.

2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents

valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.

3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is

asserted, two bits of recovered data are sent from the PHY to the MAC.

4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid

data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.

5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is

asserted, two bits of data are received by the PHY from the MAC.

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40

REV K 022412

1 2 345 6 7...54

下载PDF

与1894-40相关器件

型号	品牌	描述	获取价格	数据表
1894-40KLF	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894-40KLFT	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894419	PHOENIX	Strip Terminal Block, 12A, 1 Row(s), 1 Deck(s)	获取价格
189444-1	MACOM	COPALUM Terminals and Splices (For Solid & Stranded Aluminum or Copper Wire)	获取价格
1894448	PHOENIX	GMSTB 2,5/ 4-ST-7,62 BK	获取价格
189447-1	MACOM	COPALUM Terminals and Splices (For Solid & Stranded Aluminum or Copper Wire)	获取价格